Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-07-15
2008-07-15
Chang, Daniel D (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C333S032000, C330S144000
Reexamination Certificate
active
11473699
ABSTRACT:
An Integrated Circuits (ICs) comprising a first output stage circuit and a second output stage circuit that share common input terminals and an output terminal of the first and second output stage circuits being selectably coupled between the input terminals and the output terminal in preference to the other.
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Ritchie Charles Graeme
Seifu Fesseha Tessera
Avago Technologies Fiber IP Pte Ltd
Chang Daniel D
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