Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-11-21
2006-11-21
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S064000, C326S127000
Reexamination Certificate
active
07138822
ABSTRACT:
An integrated circuit comprising a first output stage circuit and a second output stage circuit that share common input terminals and an output terminal of the first and second output stage circuits being selectably coupled between the input terminals and the output terminal in preference to the other.
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Ritchie Charles Graeme
Seifu Fesseha Tessera
Avago Technologies Fiber (IP) Singapore Pte. Ltd.
Chang Daniel
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