Integrated circuit, and method for forming an integrated circuit

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438672, 257775, H01L 2144

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active

06107196&

ABSTRACT:
A method for forming an integrated circuit comprising providing a substrate comprising a node to which electrical connection is to be made; providing a layer of material outwardly of the node; and providing an electrically conductive plug through the layer of material and in electrical connection with the underlying node, the layer of material and conductive plug forming an interlocking discontinuity which effectively prevents displacement of the electrical conductive plug from the node. The present invention also contemplates an integrated circuit wherein an interlocking discontinuity comprises a projection which extends laterally outwardly relative to an electrically conductive plug, or a projection which extends laterally outwardly from a layer of material into an electrically conductive plug.

REFERENCES:
patent: 3717514 (1973-02-01), Burgess
patent: 4582563 (1986-04-01), Hazuki et al.
patent: 4728623 (1988-03-01), Lu et al.
patent: 4871689 (1989-10-01), Bergami et al.
patent: 4979010 (1990-12-01), Brighton
patent: 4997790 (1991-03-01), Woo et al.
patent: 5063175 (1991-11-01), Broadbent
patent: 5143861 (1992-09-01), Turner
patent: 5210054 (1993-05-01), Ikeda et al.
patent: 5219793 (1993-06-01), Cooper
patent: 5270254 (1993-12-01), Chen et al.
patent: 5286674 (1994-02-01), Roth et al.
patent: 5327011 (1994-07-01), Iwamatsu
patent: 5356836 (1994-10-01), Chen et al.
patent: 5368682 (1994-11-01), Park
patent: 5371410 (1994-12-01), Chen et al.
patent: 5378652 (1995-01-01), Samata et al.
patent: 5393702 (1995-02-01), Yang et al.
patent: 5408130 (1995-04-01), Woo et al.
patent: 5414221 (1995-05-01), Gardner
patent: 5464794 (1995-11-01), Lur et al.
patent: 5470790 (1995-11-01), Myers et al.
patent: 5510652 (1996-04-01), Burke et al.
patent: 5583380 (1996-12-01), Larsen et al.
patent: 5612252 (1997-03-01), Lur et al.
patent: 5616960 (1997-04-01), Noda et al.
patent: 5851923 (1998-12-01), Rolfson
Anonymous, IBM Tech. Disc. Bulletin, 38(6)(1995)405 "Method of Anchoring Contact or Via Plugs by Producing Lateral Recess in ILD or IMD Films"--Jun. 1995.
Anynymous, IBM Tech. Disc. Bulletin, 34(4B)(1991)228 "Rooted Refractory Metal on AL-Cu . . . "--Sep. 1991.
T. Hasegawa et al., Japan Society of Applied Physics, Proc. of 52nd Fall Meeting, 1991, p. 718 "Via Filling on Al . . . Using Al Isotropic Etching" 1991.
IBM Technical Disclosure Bulletin; Bipolar Transistor Structure With Extended Metal Base Contacts and Diffused or Implanted Emitter vol. 22, No. 5 pp. 2123-2126.
IBM Technical Disclosure Bulletin; Method of Anchoring Contact or Via Plugs by Producing Lateral Recess in ILD or IMD Films, vol. 38, No. 06, pp. 405-407.

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