Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2005-08-16
2005-08-16
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S317000
Reexamination Certificate
active
06931472
ABSTRACT:
In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by a transferring buffer which is provided on a transfer path in an on-chip bus on the LSI for temporarily storing transfer data. With this transferring buffer, even if a buffer within a slave module, specified as the destination, is fully loaded and cannot accept any more transfer, a bus master can transfer data to the transferring buffer provided on the on-chip bus. Thus, the bus master is not kept waiting for execution of a transfer, irrespective of the state of the buffer within the slave, thereby improving the processing performance of the entire system.
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Kondo Nobukazu
Noguchi Kouki
Nonomura Itaru
Suzuki Kei
Antonelli, Terry, Stout & Kraas, LLP
Dang Khanh
Renesas Technology Corp.
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