Integrated circuit and fabricating method and evaluating method

Details Integrated circuit and fabricating method and evaluating method Integrated circuit and fabricating method and evaluating method

1997-05-29

1999-11-30

Tran, Minh Loan

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

257773, 257777, 257698, H01L 2358, H01L 2348, H01L 2304

Patent

active

059947160

ABSTRACT:
A method of fabricating an integrated circuit of which a bonding condition can be evaluated simply is provided. Two external connecting electrodes are provided on the surface, via holes are formed below them, and conductive portions are formed in the via holes. Then, a first metal film is formed on a rear face of a chip and a second metal film is formed on a surface of a ceramic substrate, and then both of them are made contact and heated so as to bond the chip and the ceramic substrate. Further, when the first metal film is formed, a slit portion which no first metal film exists is provided. When the bonding condition is evaluated, a resistance between two external connecting electrodes is measured.

REFERENCES:
patent: 5158911 (1992-10-01), Quentin
patent: 5512710 (1996-04-01), Schroeder

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