Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-03-06
2007-03-06
Chu, Gabriel L. (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S726000, C714S727000
Reexamination Certificate
active
10402034
ABSTRACT:
An integrated circuit (“IC”) comprising a plurality of logic modules. The IC further comprises a plurality of bus segments each associated with one of the logic modules; a debug bus interconnecting the bus segments in a ring; and a debug port connected to the debug bus for accessing debug data on the debug bus. Each bus segment takes in data from the logic module associated therewith and outputs the data to the debug bus to be forwarded to the next bus segment along the ring.
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Bart Vermeulen and Sandeep Kumar Goel, “Design for Debug: Catching Design Errors in Digital Chips”, IEEE Design & Test of Computers; May-Jun. 2002; pp. 37-45.
Chu Gabriel L.
Hewlett--Packard Development Company, L.P.
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