Integrated circuit

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Details

C714S726000, C714S727000

Reexamination Certificate

active

10402034

ABSTRACT:
An integrated circuit (“IC”) comprising a plurality of logic modules. The IC further comprises a plurality of bus segments each associated with one of the logic modules; a debug bus interconnecting the bus segments in a ring; and a debug port connected to the debug bus for accessing debug data on the debug bus. Each bus segment takes in data from the logic module associated therewith and outputs the data to the debug bus to be forwarded to the next bus segment along the ring.

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Examination Report Under Section 18(3) from the UK Patent Office dated Jul. 29, 2005; 3 pages.
Search Report Under Section 17(5): Jul. 16, 2004; 3 pages.
Bart Vermeulen and Sandeep Kumar Goel, “Design for Debug: Catching Design Errors in Digital Chips”, IEEE Design & Test of Computers; May-Jun. 2002; pp. 37-45.

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