Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With electrical contact in hole in semiconductor
Patent
1994-09-02
1997-06-03
Wojciechowicz, Edward
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With electrical contact in hole in semiconductor
257503, 257514, 257515, 257519, 257520, 257774, 257544, H01L 2904
Patent
active
056357532
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to an integrated circuit having at least two active components, such as transistors.
STATE OF THE ART
Integrated circuits of this type are common knowledge and are manufactured on a large scale in various "MOS" and/or bipolar technology.
Presently, attempts are being made to further reduce the size of circuit structures in order to, on the one hand, increase packing density and, on the other, to raise elementary frequency.
In conventional CMOS technology, a number of problems arise, in particular, when attempting to manufacture scaled down design schemes in the submicrometer structural region. It must be kept in mind that the typical structural size of circuits presently in production is in the order of about 0.8 .mu.m, whereas the typical structural size of circuits presently under development is intended to be in the order of about 0.4 .mu.m.
Examples of these scaling problems are:
1. CMOS transistors that switch faster and have a greater bandwidth have to be manufactured by reducing the lateral and vertical structural dimensions. This demands many compromises resulting in, e.g., not ideally quadrupling the circuit speed when halving the channel length, but rather just in increasing the circuit speed to, in some instances, less than 50%. Simultaneously, the internal amplification of the transistors decreases practically linearly to the reduction in structural dimensions so that these transistors and circuits are no longer suitable for rapid analog circuits.
2. The increased packing density aggravates parasitic effects, such as cross-talk, latch-up and voltage fluctuations on the supply lines with the circuit signal-to-noise ratio simultaneously becoming smaller.
3. Scattering of the electric transistor parameters is usually dependent on the width variations of the structuring parameters which in the event of small signal-to-noise ratios and strong cross-talk threatens digital circuits and makes rapid analog CMOS circuits impossible.
4. Reduction of the lateral structural dimensions if the thickness of the layers cannot be correspondingly reduced results in an increase in contact and transition resistances and, if the current densities increase simultaneously, in ageing and failure problems occurring in the circuits due to material transport and metallurgical alterations in the interfaces of the material (e.g., between silicon and metallizations), including electromigration.
An integrated semiconductor circuit composed of a substrate having a conductive layer on the back surface of the substrate and multiple semiconductor layers on the front surface of the substrate is described in U.S. Pat. No. 5,065,216. Very special conductive paths are provided with which the supply voltages can be led from the back side of the circuit to the active elements.
U.S. Pat. No. 4,631,570 discloses an integrated circuit which discloses hidden oxide isolations and a substrate having negligible resistance which is suitable for connecting.
An isolation structure composed of double and hidden oxide layers is presented in the article "Electronic Letters", vol. 25, no. 16, 3 Aug. 1989, pages 1071-1072)" In this case, the SIMOX concept is utilized. SIMOX n.sup.30 substrates are, however, less suitable due to the poor quality of their oxide bottom side.
The presented state of the art has in common that no highly conductive substrate is provided to which a pole of a supply source is connected, that there is no electrical isolation due to a dielectric isolation layer between the highly conductive substrate and the semiconductor layer, and that the fabrication of the epitaxial layers occurs in an unfavorable sequence of layers.
Moreover, the substrates of the cited documents possess no "active" function for the top transistors, due to which possible simplification of realization of the circuits in the state of the art is not considered.
DESCRIPTION OF THE INVENTION
The object of the present invention is to provide an integrated circuit having at least two active components, permitti
REFERENCES:
patent: 4631570 (1986-12-01), Birrittella et al.
patent: 4819052 (1989-04-01), Hutter
patent: 5065216 (1991-11-01), Suzuki et al.
Dudek Volker
Hofflinger Bernd
Hofflinger Bernd
Wojciechowicz Edward
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