Integrated circuit

Details Integrated circuit Integrated circuit

1997-08-15

2000-09-05

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

711167, 711219, 714719, G06F 1200

Patent

active

06115783&

ABSTRACT:
In order to precisely measure the speed of memory unit, the memory unit stores at least one bit data at a predetermined bit position at each memory word such that the logical value of the one bit data changes alternately in order of memory address. An address increment circuit, which is provided in a module including the memory unit, successively generates memory addresses which are applied to the memory. The address increment circuit increments a memory address in response to the output of the memory. The memory speed between two consecutive memory outputs is detected by measuring a pulse width of a pulse signal outputted from the memory unit. Thus, a relatively large delay otherwise caused at a buffer amplifier can effectively be compensated.

REFERENCES:
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patent: 5636225 (1997-06-01), Osawa
patent: 5704035 (1997-12-01), Shipman
patent: 5892776 (1999-04-01), Kumakura
patent: 5910181 (1999-06-01), Hatakenaka et al.
IBM Technical Disclosure Bulletin, vol. 32, No. 4A, Pg. 434/435, "Performance Self-Test for High Performance Random-Access Memories", dated Sep. 1989.

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