Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2002-01-22
2004-10-05
Elms, Richard (Department: 2324)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S701000, C257S737000, C257S778000, C438S107000, C438S108000
Reexamination Certificate
active
06800941
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90133092, filed Dec. 31, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated chip package structure and method of manufacture the same. More particularly, the present invention relates to an integrated chip package structure and method of manufacture the same using ceramic substrate.
2. Description of Related Art
In the recent years, the development of advanced technology is on the cutting edge. As a result, high-technology electronics manufacturing industries launch more feature-packed and humanized electronic products. These new products that hit the showroom are lighter, thinner, and smaller in design. In the manufacturing of these electronic products, the key component has to be the integrated circuit (IC) chip inside any electronic product.
The operability, performance, and life of an IC chip are greatly affected by its circuit design, wafer manufacturing, and chip packaging. For this present invention, the focus will be on chip packaging technique. Since the features and speed of IC chips are increasing rapidly, the need for increasing the conductivity of the circuitry is necessary so that the signal delay and attenuation of the dies to the external circuitry are reduced. A chip package that allows good thermal dissipation and protection of the IC chips with a small overall dimension of the package is also necessary for higher performance chips. These are the goals to be achieved in chip packaging.
There are a vast variety of existing chip package techniques such as ball grid array (BGA), wire bonding, flip chip, etc. . . . for mounting a die on a substrate via the bonding points on both the die and the substrate. The inner traces helps to fan out the bonding points on the bottom of the substrate. The solder balls are separately planted on the bonding points for acting as an interface for the die to electrically connect to the external circuitry. Similarly, pin grid array (PGA) is very much like BGA, which replaces the balls with pins on the substrate and PGA also acts an interface for the die to electrically connect to the external circuitry.
Both BGA and PGA packages require wiring or flip chip for mounting the die on the substrate. The inner traces in the substrate fan out the bonding points on the substrate, and electrical connection to the external circuitry is carried out by the solder balls or pins on the bonding points. As a result, this method fails to reduce the distance of the signal transmission path but in fact increase the signal path distance. This will increase signal delay and attenuation and decrease the performance of the chip.
Wafer level chip scale package (WLCSP) has an advantage of being able to print the redistribution circuit directly on the die by using the peripheral area of the die as the bonding points. It is achieved by redistributing an area array on the surface of the die, which can fully utilize the entire area of the die. The bonding points are located on the redistribution circuit by forming flip chip bumps so the bottom side of the die connects directly to the printed circuit board (PCB) with micro-spaced bonding points.
Although WLCSP can greatly reduce the signal path distance, it is still very difficult to accommodate all the bonding points on the die surface as the integration of die and internal devices gets higher. The pin count on the die increases as integration gets higher so the redistribution of pins in an area array is difficult to achieve. Even if the redistribution of pins is successful, the distance between pins will be too small to meet the pitch of a printed circuit board (PCB).
SUMMARY OF THE INVENTION
Therefore the present invention provides an integrated chip package structure and method of manufacturing the same that uses the original bonding points of the die and connect them to an external circuitry of a thin-film circuit layer to achieve redistribution. The spacing between the redistributed bonding points matches the pitch of a PCB.
In order to achieve the above object, the present invention presents an integrated chip package structure and method of manufacturing the same by adhering the backside of a die to a ceramic substrate, wherein the active surface of the die has a plurality of metal pads. A thin-film circuit layer is formed on top of the die and the ceramic substrate, where the thin-film circuit layer has an external circuitry that is electrically connected to the metal pads of the die. The external circuitry extends to a region that is outside the active area of the dies and has a plurality of bonding pads located on the surface layer of the thin-film layer circuit. The active surface of the die has an internal circuitry and a plurality of active devices, where signals can be transmitted from one active device to the external circuitry via the internal circuitry, then from the external circuitry back to another active device via the internal circuitry. Furthermore, the ceramic substrate has at least one inwardly protruded area so the backside of the die can be adhered inside the inwardly protruded area and exposing the active surface of the die. Wherein the ceramic substrate is composed of a ceramic layer and a heat conducting material formed overlapping and the inwardly protruded areas are formed by overlapping the ceramic substrate with openings on the heat conducting layer. Furthermore, the present chip package structure allows multiple dies with same or different functions to be packaged into one integrated chip package and permits electrically connection between the dies by the external circuitry.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6271469 (2001-08-01), Ma et al.
patent: 6521996 (2003-02-01), Seshan
patent: 2003/0201548 (2003-10-01), Ikezawa et al.
Huang Ching-Cheng
Lee Jin-Yuan
Lin Mou-Shiung
Elms Richard
J.C. Patents
Megic Corporation
Wilson Christian D.
LandOfFree
Integrated chip package structure using ceramic substrate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated chip package structure using ceramic substrate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated chip package structure using ceramic substrate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3298388