Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-02-14
2001-12-18
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C714S006130, C712S227000
Reexamination Certificate
active
06331957
ABSTRACT:
BACKGROUND
1. Field
The present disclosure pertains to the field of integrated circuits. More particularly, the present disclosure pertains to the field of testability and internal observation techniques for an integrated circuit.
2. Description of Related Art
As integrated circuit complexity continues to rise, the ability to track the internal sequencing of operations continues to drop. This loss of visibility into the inner workings of an integrated circuit such as a processor disadvantageously complicates the process of debugging problems encountered while executing programs. Accordingly, improving visibility may desirably assist those writing or debugging some software programs or the integrated circuit hardware itself.
Visibility into internal operations of processors often decreases due to features of such processors that further distance externally visible bus or other transactions from activities of inner processing engine(s). Such features may advantageously improve processor throughput but may have the unfortunate side effect of decreasing internal visibility. For example, modern processors speculatively execute strings of instructions after a branch instruction before it is known whether the branch will be taken. To an external observer, such speculative execution is misleading as to the actual flow of execution undertaken by the processor when branch mispredicts occur. Thus, the internal instruction pipeline becomes increasing detached from the memory execution engine.
Furthermore, modern bus interface units themselves may employ sophisticated bus transaction protocols which complicate attempts to decipher even the string of transactions occurring on the bus. For example, the Pentium® Pro Processor, the Pentium® II Processor, and the Pentium® III Processor from Intel Corporation of Santa Clara, California employ a heavily pipelined, token-based front side bus (FSB) protocol that allows deferred transaction replies. This type of split transaction bus eliminates the former address/data sequencing that allowed simple association of memory data to particular addresses based on the bus contents. Instead, data from various different requests may appear on the bus in a different order than the requests. Moreover, data may be returned many clocks after the request is completed. Thus, even viewing the external bus itself provides limited insight into the operation of the processor.
Prior art techniques that improve internal visibility include the use of scan chains and breakpoint registers. Scan chains provide information about a number of internal nodes. Traditional scan chains do not provide an automatic triggering mechanism based on internal state. Typical scan chains report internal state at an externally determined point in time rather than due to the occurrence of particular internal events. Breakpoint registers cause a processor to stop execution when an internal instruction pointer reaches a value programmed in a breakpoint register. Breakpoint techniques, however, track the state of the pipeline, reporting when a particular instruction is being executed but not the data operated on by that instruction. Thus, breakpoint techniques do not adequately improve the ability to observe values being generated by instructions, nor do they provide visibility into memory access content and sequencing, cache utilization, external snooping, or other cycles typically issued to the FSB.
Additionally, prior art techniques to observe even externally visible buses are becoming inadequate. An externally visible bus is a bus which appears on a circuit board or other inter-component medium. In other words, it is a bus between two components. Probes which intercept these signals are increasingly invasive as the sensitivity to even minor load changes may confound or even cause problems. Moreover, some probing devices may not be able to capture data at a sufficiently rapid rate to actually analyze signals on some high-speed buses. Unfortunately, slowing down the bus to allow signal capture and analysis may also confound, remove, or cause problems.
Thus, prior art techniques are becoming increasingly inadequate. For integrated circuits that have high speed external buses, prior art bus signal observation techniques are exhibiting frequency-related limitations. For integrated circuits that additionally or alternatively have important buses integrated within the integrated circuit, prior art internal observation techniques may not provide sufficient visibility into memory operations. These problems are generally compounded by increasing levels of integration and increasing bus frequencies.
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Kurts Tsvika
Nathan Ofer J.
Zavertnik John M.
Draeger Jeffrey S.
Intel Corporation
Le Vu A.
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