Patent
1984-03-16
1988-11-08
James, Andrew J.
357 46, 357 34, 357 36, 357 43, 357 234, 357 86, H01L 2702
Patent
active
047836946
ABSTRACT:
The safe operating area can be increased and the die area can be decreased for a monolithic Darlington circuit employing an MOS input transistor and bipolar output transistor by subdividing the bipolar transistor into a multiplicity of rectangular spaced apart bipolar device regions, each of which is surrounded by an annular shaped MOS device region. The source and channel of the MOS devices are formed in an extension of the base of the bipolar devices. The substrate serves as a common collector for all the bipolar device regions and as a common drain for all the MOS device regions. The gate electrode, which runs over the interstices between the parallel spaced apart bipolar device areas is covered by an insulator so that the emitter metallization may extend substantially over the entire upper surface of the die. A more compact layout and better thermal coupling between the MOS and bipolar devices are obtained. These features reduce the total die area and improve the thermal stability of the circuit.
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Merrill Perry L.
Stoltenburg Rodney R.
Handy Robert M.
James Andrew J.
Mintel William A.
Motorola Inc.
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