Integrated bipolar-CMOS circuit isolation for providing differen

Details Integrated bipolar-CMOS circuit isolation for providing differen Integrated bipolar-CMOS circuit isolation for providing differen

1987-05-28

1989-04-25

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 48, 3072962, 3072967, H01L 2702

Patent

active

048252751

ABSTRACT:
Disclosed is a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.

REFERENCES:
patent: 3999213 (1976-12-01), Brandt et al.
patent: 4327368 (1982-04-01), Uchida
patent: 4484388 (1984-11-01), Iwasaki
patent: 4546370 (1985-10-01), Cunan
patent: 4647956 (1987-03-01), Shrivastava et al.
patent: 4670668 (1987-06-01), Liu

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