Patent
1990-02-20
1991-11-12
Hille, Rolf
357 43, 357 48, 357 59, 357 71, H01L 2972, H01L 2704, H01L 2904, H01L 2348
Patent
active
050652087
ABSTRACT:
A process is disclosed with integrated steps for fabricating bipolar and CMOS transistors. Mask, patterning and implanting steps are highly integrated to reduce the fabrication complexity. The integrated steps include a split level polysilicon step wherein PMOS and NMOS gate conductors and a bipolar emitter structure is formed. The polysilicon is heavily doped which forms MOS transistor gate electrodes, and another high impurity concentration area which is later diffused into an underlying bipolar base region. Small area, high performance transistors can be fabricated with laterally extending contact strips. Alignment of electrode metallization patterns is thus less critical.
REFERENCES:
patent: 4481706 (1984-11-01), Roche
patent: 4484211 (1984-11-01), Takemoto et al.
patent: 4539742 (1985-09-01), Kanzaki et al.
patent: 4583106 (1986-04-01), Anantha et al.
patent: 4811076 (1989-03-01), Tigelaar et al.
Shah Rajiv R.
Tran Toan
Comfort James T.
Hille Rolf
Limanek Robert P.
Merrett N. Rhys
Sharp Melvin
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