Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2002-10-08
2004-05-18
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S158000, C327S272000, C327S274000
Reexamination Certificate
active
06737901
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrable, controllable delay device having an input connection for an input signal which is to be delayed, an output connection for a delayed output signal, and a control connection for a control signal which controls the delay time. The invention also relates to use of such an integrable, controllable delay device. Finally, the invention relates to a method in order to delay a clock signal, using such a delay device.
Such integrable, controllable delay devices are widely used for delaying a clock signal in integrated semiconductor circuits. One particular application of the delay device is in a delay control loop. Delay control loops are used in digital circuits in order to produce clock signals at a specific phase angle. By way of example, synchronously operated integrated semiconductor memories, which operate on the double data rate principle, so-called DDR SDRAMs (double data rate synchronous random access memories) use a delay control loop in order, taking account of internal signal delay times, to produce a clock signal on the output side, which produces data that is to be emitted, in synchronism with an input clock signal which is supplied to the integrated circuit at some other point.
A delay control loop compares the clock signal which is supplied to the input side of the delay unit with the delayed clock signal which is produced on the output side, and readjusts the delay as a function of the phase difference until the phase difference is regulated as closely as possible to zero. It is particularly important for the clock on the output side to be as stable as possible and to be free of jitter. For example, the clock on the output side is intended to be influenced as little as possible by fluctuations in the supply voltage, and its current delay time setting is intended to be independent of the drive to the delay unit.
One known delay device is in the form of a so-called tapped delay line. In this case, inverters are connected in series. The signal that is delayed along the delay line can be tapped off via signal paths which branch off from the delay line. The signal paths are coupled to a common node on the output side. These branching signal paths each contain a tristate inverter, which either passes on the signal which is to be delayed, or is switched to produce a high impedance. The output-side node has a high capacitance, which is proportional to the number of inverter stages in the delay line. The tristate inverters switch relatively slowly. Once the signal has been tapped off from the chain of inverters, it is also necessary to take account of the signal delay produced by the tristate inverter and any inverter which there may be downstream. Finally, an inverter in the delay line has to drive two input loads which are connected to it on the output side, namely the downstream inverter in the delay line, and the input of the tapping tristate inverter.
European patent EP 0 570 158 B1 (DE 693 27 612 T2) and U.S. Pat. Nos. 5,336,939 and 5,359,232 disclose a circuit for producing a stable clock signal on the basis of frequency multiplication. The circuit contains a delay stage with a variable delay time, wherein two multiplexers are connected in series. A signal is supplied firstly without any delay and secondly via delay elements as well, to the input sides of the multiplexers.
U.S. Pat. No. 6,329,854 B1 and the corresponding German patent application DE 199 12 967 A1 disclose a delay control loop with a delay path wherein multiplexers are provided, whose input connections can be connected to one another via flipflops. All the multiplexers are driven at the same time, either by an UP control signal or by a DOWN control signal.
U.S. Pat. No. 5,465,076 and the corresponding German patent application DE 43 27 116 A1 disclose a programmable delay line, wherein multiplexers are used to whose inputs an input signal can be supplied directly and, in addition, with a delay.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrable and controllable delay unit, its utilization in a control loop, and a signal delay method, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the delay device has a delay time that can be set as exactly as possible, so that a largely stable, jitter-free output clock can be produced when this delay device is used in a delay control loop. In particular, the output clock is intended to be as independent as possible of manufacturing-dependent fluctuations in the component parameters, supply voltage fluctuations or temperature fluctuations.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrable, i.e., integratable, controllable delay device, comprising:
an input terminal for receiving an input signal to be delayed;
an output terminal for outputting an output signal delayed with respect to the input signal;
a control connection for receiving a control signal controlling a delay time;
a multiplicity of multiplexers each having a first input, a second input, and an output connection;
the multiplexers forming a series circuit with downstream multiplexers and upstream multiplexers in a signal flow direction, with the second connection of a respective downstream multiplexer connected to the output of a respective upstream multiplexer, and the first connection of each the multiplexer connected to the input; and
the second connection of one of the multiplexers being connected to reference potential, and the output of another of the multiplexers being coupled to the output terminal.
In other words, the objects are achieved by an integrable, controllable delay device which comprises an input connection for an input signal which is to be delayed, an output connection for a delayed output signal, a control connection for a control signal which controls the delay time; a large number of multiplexers each having a first and a second input connection and one output connection, with the multiplexers being connected in series by connecting the second connection of a downstream multiplexer to the output of an upstream multiplexer and by coupling the first connections of all the multiplexers to the input connection, with the second connection of one of the multiplexers being connected to a connection for a reference potential, and the output of another of the multiplexers being coupled to the output connection.
With the above and other objects in view there is also provided, in accordance with the invention, the above-outlined delay device in combination with a delay control loop. The delay device is connected in the delay control loop such that a delay time of the delay device is readjusted in dependence on a phase difference between a clock signal input to the delay device and an output signal carried at the output of the delay device.
With the above and other objects in view there is also provided, in accordance with the invention, a method for delaying a clock signal. The method comprises the following steps:
providing an integrable, controllable delay device according to the above summary;
inputting the clock signal to be delayed at the input terminal and providing a control signal formed with a number of bits at the control connection of the delay device;
setting a switch position of two series-connected multiplexers in dependence on the bits of the control signal such that a connection is established in each case for passing on the clock signal to be delayed between the first signal input and the output connection of the two multiplexers;
setting a switch position of all other multiplexers such that a signal connection is produced between the second input connection and the output connection thereof;
outputting a delayed clock signal at the output terminal of the multiplexer connected last in the series circuit;
defining a phase difference between a first signal derived from the clock signal to be delayed and a second s
Hein Thomas
Heyne Patrick
Cunningham Terry D.
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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