Insulator-compound semiconductor interface structure

Details Insulator-compound semiconductor interface structure Insulator-compound semiconductor interface structure

1997-03-04

2002-03-19

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S014000, C257S183000, C257S192000, C257S410000, C257S411000

Reexamination Certificate

active

06359294

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to insulator-compound semiconductor interfaces and fabrication thereof and more specifically to insulator-compound semiconductor interfaces in semiconductor devices.
BACKGROUND OF THE INVENTION
Insulator-semiconductor interfaces are the workhorse of the semiconductor industry. Insulator and interface stability as well as reliability are affected by degradation of the insulator material and the insulator-semiconductor interface. For compound semiconductors, functional insulator III-V semiconductor interfaces are fabricated by in-situ deposition of a specific insulating layer (e.g. gallium oxide such as Ga
2
O
3
) on gallium arsenide (GaAs) based semiconductor epitaxial layers while maintaining an ultra-high vacuum (UHV). Full accessibility of the GaAs band gap and interface state densities in the low 10
10
cm
−2
eV
−1
have been demonstrated. For compound semiconductors (e.g. GaAs), the remaining problems are associated with stability and reliability issues including carrier injection, charge trapping, and eventually, oxide degradation and breakdown. Trap densities as high as 2×10
12
cm
−2
have been found in e-beam deposited Ga
2
O
3
films causing long term drift of device parameters in accumulation and inversion. See for instance, M. Passlack et al., Appl. Phys. Lett., vol 68, 1099 (1996), Appl. Phys. Lett., vol. 68, 3605 (1996), and Appl. Phys. Lett., vol 69, 302, (1996). One method of forming the specific insulating layer is described in U.S. Pat. No. 5,451,548, entitled “Electron beam Deposition of gallium oxide thin films using a single purity crystal layer”, issued Sep. 19, 1995.
So far, insulator and interface stability and reliability have only been extensively investigated for the SiO
2
—Si system. Degradation and damage were found to scale with the integrated flux of hot carriers (excluding the ultrathin oxide regime). Interface microroughness and defects facilitate localized injection of carriers from the substrate causing accelerated degradation. The degradation is further enhanced by weak or strained bonds, defects, contaminants, etc. located in the interfacial region which are preferred targets of degradation due to injected carriers. Eventually, damage induced by injected carriers causes breakdown of the insulator-semiconductor system. See for instance, D. A. Buchanan et al., Proc. Electrochemical Society, vol 96-1, p. 3; M. Depas et al., Proc. Electrochemical Society, vol. 96-1, p. 352. For Si technology, less degradation is achieved by sophisticated Si surface cleaning techniques and by replacing strained Si—O or weak Si—H interface bonds by stronger Si—N bonds at the insulator-semiconductor interface. See for instance, H. Fukuda et al. Proc. Electrochemical Society, vol. 96-1, P. 15; P. Morfouli et al., IEEE Electr. Dev, Lett., 17, 328 (1996); and A Malik et al., J. Appl. Phys., 79, 8507 (1996).
For compound semiconductors, the insulator-compound semiconductor structure is different and even more complex with respect to stability and reliability issues. Unlike thermal SiO
2
, the specific insulating layer is fabricated by deposition on a semiconductor surface. Since charge trapping is more pronounced in the deposited layer than in the thermal SiO
2
, additional stability and reliability problems arise. Further, the microroughness of a deposited insulator-compound semiconductor interface is typically inferior to the thermal oxide-Si interface. Unlike Si, the compound semiconductor surface is composed of at least two different types of surface atoms adding significant complexity to the atomic interfacial structure and extra potential sources for defects and weak bonds. The intentional replacement of specific atoms in specific bonds after fabrication of the interfacial structure appears to be an insurmountable task. Thus, prior art techniques applied to enhance stability and reliability in Si technology do not succeed for compound semiconductors.
Prior art III-V epitaxial wafer production employs a semiconductor layer to complete the epitaxial structure. Various semiconducting top layers are being used, for example GaAs, In
1−x
Ga
x
As, Al
1−x
Ga
x
As, InGaAsP, etc., depending on the specific device/circuit application and semiconductor substrate. The use of semiconducting top layers in prior art epitaxial wafer production results in uncontrollable and detrimental electrical and chemical surface properties. Electronic and optoelectronic device/circuit processing is complicated and device/circuit performance is affected. The degree of complication and degradation is subject to the particular device/circuit processing and application. For example, the fabrication and performance of unipolar transistor devices/circuits is hampered by plasma exposure, Fermi level pinning, and instability of the gate-source and gate-drain regions. The fabrication of functional and stable MOSFET devices has been impossible.
Uncontrollable and detrimental electrical and surface properties are caused by chemical surface reactions resulting in the formation of native oxides and dangling bonds. In turn, the surface is rendered thermodynamically unstable and exhibits a pinned Fermi level. Specifically, the high GaAs surface reactivity induces Fermi level pinning and surface instability after surface exposure as small as 10
3
Langmuirs (1 Langmuir=10
−6
Torr). Surface preparation techniques conducted after exposure to air (sulfur, selenium, etc.) have proven to be inefficient and unstable.
Accordingly, it would be highly advantageous to provide new interfaces and methods of fabrication which overcome these problems.
It is a purpose of the present invention to provide a new and improved insulator-compound semiconductor interface structure.
It is another purpose of the present invention to provide a new and improved insulator-compound semiconductor interface structure with improved stability and reliability.
It is still another purpose of the present invention to provide a new and improved insulator-compound semiconductor interface structure which is relatively easy to fabricate and use.
It is yet another purpose of the present invention to provide a new and improved insulator-compound semiconductor interface structure which can be formed in situ to further reduce impurities and to further simplify fabrication.
It is a further purpose of the present invention to provide a new and improved insulator-compound semiconductor interface structure in which carrier density at the deposited insulator-compound semiconductor interface is orders of magnitude less than in the channel.
It is a still further purpose of the present invention to provide a new and improved insulator-compound semiconductor interface structure in which the probability of injecting hot carriers into the insulator is reduced by orders of magnitude.
It is yet a further purpose of the present invention to provide a new and improved insulator-compound semiconductor interface structure in which the effect of stress induced interface states located close to the semiconductor band edges is minimized.
It is still a further purpose of the present invention to provide a new and improved insulator-compound semiconductor interface structure in which effects of Coulomb scattering and interface roughness scattering are minimized for carriers in the inversion/accumulation channel.
SUMMARY OF THE INVENTION
The above problems and others are at least partially solved and the above purposes and others are realized in an insulator-compound semiconductor interface structure including compound semiconductor material with a spacer layer of semiconductor material having a bandgap which is wider than the bandgap of the compound semiconductor material positioned on a surface of the compound semiconductor material and an insulating layer positioned on the spacer layer. Minimum and maximum thicknesses of the spacer layer are determined by the penetration of the carrier wave function into the spacer layer and by the desired device performance.
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