Insulating layers and a forming method thereof

Details Insulating layers and a forming method thereof Insulating layers and a forming method thereof

1999-05-25

2000-12-26

Booth, Richard

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438622, 438633, 438637, 438778, 438780, H01L 2906, H01L 2358, H01L 2940

Patent

active

061658936

ABSTRACT:
The present invention relates to insulating layers and a forming method thereof, more particularly, to planarized insulating layers among wires on the same insulating layer or different layers and a forming method thereof which minimize parasitic capacitance generated from the wires, prevent via poison and reduce step difference between the adjacent layers by forming a dielectric layer having a low dielectric constant between the wires patterned in the same layer and by forming an insulating interlayer having excellent heat-dissipation efficiency and interface-adhesiveness between the wires in the different layer. The present invention includes an insulated substrate, an insulating interlayer on the insulated substrate, a plurality of first wires on the insulating interlayer, a first insulating layer formed only on upper surfaces of a plurality of the first wires, a second insulating layer filling up valleys between the first wires and the first insulating layer wherein surfaces of the first and second insulating layers lie on a same plane, a third insulating layer on the surfaces of the first and second insulating layer, a plurality of second wires on the third insulating layer, and a plurality of plugs connecting the first wires electrically to the second wires, the plugs formed through the first and third insulating layer.

REFERENCES:
patent: 5858870 (1999-01-01), Zheng et al.
patent: 6025230 (2000-02-01), Hshieh et al.
patent: 6037253 (2000-03-01), Chung
N. Oda et al.; 0.6 .mu.m Pitch Highly Reliable Multilevel Interconnection Using Hydrogen Silicate Based Inorganic SOG for Sub-Quarter Micron CMOS Technology; 1997 Symposim on VLSI Technology Digest of Technical Papers; pp. 79-80.
Juseon Goo et al.; Reliable and Simple Non-Etch Back Process for Intermetal Dielectric (IMD) of 256M DRAM Using Spin-on Hydrogen Silsesquioxane (HSQ); Feb. 10-11, 1997 DUMIC Conference; pp. 329-332.
J. Waeterloos et al; "Integrating a hydrogen silsesquioxane spin-on dielectric in a quarter micron technology;" Feb. 10-11, 1997 DUMIC Conference; pp. 310-316.

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