Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-05
2002-12-31
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S332000, C257S335000, C257S336000, C257S339000, C257S341000, C257S342000, C257S343000
Reexamination Certificate
active
06501128
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an insulate gate transistor that has an insulated gate structure formed of a metal layer, an oxide layer and a semiconductor layer.
BACKGROUND
FIG. 10
is a cross sectional view of the unit structure (the so-called “half cell”) of a conventional insulate gate bipolar transistor (hereinafter referred to as an “IGBT”), that is a type of insulate gate transistor. Referring now to
FIG. 10
, a p-type well region
4
is in the surface portion of an n-type drift layer
3
. A heavily doped p
+
-type contact region
5
is in p-type well region
4
. An n-type emitter region
6
is in the surface portions of p-type well region
4
and p
+
-type contact region
5
. A gate electrode
7
is above the semiconductor structure with a gate oxide film
10
interposed therebetween from n-type emitter region
6
to n-type emitter regions
6
of the adjacent unit structure. An emitter electrode
9
is in common contact with n-type emitter region
6
and p
+
-type contact region
5
. A collector layer
2
is on the back surface of n-type drift layer
3
. A collector electrode
1
is on the back surface of collector layer
2
. Emitter electrode
9
is extended above gate electrode
7
with an interlayer insulation film
8
interposed therebetween.
FIG. 11
shows cross sectional views explaining the steps
11
(
a
) through
11
(
f
) for manufacturing the IGBT of FIG.
10
. In
FIG. 11
, only the emitter side of the IGBT is shown for the sake of simplicity. Referring now to the cross section (a) of
FIG. 11
, a thin gate oxide film
10
is formed on n-type drift layer
3
by thermal oxidation. A polycrystalline silicon film is deposited on gate oxide film
10
, and a gate electrode
7
is formed by patterning the deposited polycrystalline silicon film by photolithography. As shown in FIG.
11
(
b
), boron ions
14
a
are selectively implanted using gate electrode
7
as a mask. The implanted boron atoms are designated by a reference numeral
14
b
. Referring now to FIG.
11
(
c
), a p-type well region
4
is formed by activating implanted boron atoms
14
b
by a heat treatment. Boron ions
15
a
are selectively implanted using a patterned photoresist
11
as a mask for the ion implantation as shown in FIG.
11
(
d
). The implanted boron atoms are designated by a reference numeral
15
b
. Referring now to FIG.
11
(
e
), arsenic ions
16
a
are implanted using gate electrode
7
and a patterned photoresist
12
as masks for the ion implantation. The implanted arsenic atoms are designated by a reference numeral
16
b
. As shown in FIG.
11
(
f
), p
+
-type contact region
5
and n-type emitter region
6
are formed by activating the implanted boron atoms
15
b
and the implanted arsenic atoms
16
b
by a heat treatment. According to the manufacturing method described above, p-type well region
4
and n-type emitter region
6
are self-aligned by ion implantation using the same gate electrode
7
as a mask for defining one end of p-type well region
4
and one end of n-type emitter region
6
.
In the IGBT exhibiting the breakdown voltage of the 600 V class, p-type well region
4
is 4 &mgr;m in depth, p
+
-type contact region
5
is 3 &mgr;m in depth, and n-type emitter region
6
is 0.3 &mgr;m in depth. And, the width of the surface portion of p-type well region
4
between n-type emitter region
6
and n-type drift layer
3
, that is the channel length, is about 1 &mgr;m.
Recently, the diffusion depth of the p-type well region has become reduced to reduce the loss of the IGBT (cf. M. Otsuki, et. al., “The 3rd generation IGBT toward a limit of IGBT performance”, Proc. ISPSD '93, pp. 24-29, (1993), and T. Kushida, et. al., “A He irradiated IGBT with a shallow p-base and shallow FLRs”, Proc. ISPSD ′97, pp. 277-280, (1997)).
However, when the diffusion depth of the p-type well region is limited to be shallow, the lateral diffusion length is shortened, resulting in a shortened channel length. Due to the shortened channel length, the current caused by short-circuiting of the load (load short-circuit current) is increased and, therefore, the short circuit withstand capability of the device is reduced.
Various countermeasures have been proposed to obviate the above described problem and to secure a certain short circuit withstand capability. The proposed countermeasures include patterning the emitter structure for shortening the channel length in the MOS structure (cf. Akio Nakagawa, DE 3 519 389 A1) and combining n-type and n
+
-type impurity distributions for forming the emitter region (J. Zeng, et. al., “Design of IGBTs for Latch-up Free Operation”, Solid State Electronics vol. 37, No. 8, pp. 1471-1475, (1994), and Kenji Suzuki, EP 0 336 393 A2).
The countermeasures described above, however, obtain a sufficient short circuit withstand capability at the sacrifice of on-state voltage drop of the device. Although the electrons injected into the n-type drift layer of the IGBT may be controlled, the above described countermeasures are not so effective to improve the latch-up withstand capability of the npn transistor formed of an n-type emitter region, a p-type well region and an n-type drift layer. Due to the unimproved latch-up withstand capability, it is impossible to prevent the parasitic npnp thyristor, formed of n-type emitter region
6
, p-type well region
4
, n-type drift layer
3
and p-type collector layer
2
, from latching up.
In the ON-state of the IGBT, the injected electron current Id (in the saturation region) is expressed by the following equation.
Id=
(
Z/L
)&mgr;
Co
(
Vg−Vth
)
2
Eq. (1)
Here, Z is the circumferential length of the channel region, L the channel length, Co the gate capacitance, Vg the gate voltage and Vth the threshold value.
The IGBT is a device that uses the injected electron current as a base current to drive the pnp transistor formed of p-type well region
4
, n-type drift layer
3
and p-type collector layer
2
. The on-voltage of the IGBT has been reduced so far by increasing Z, by shortening L and by lowering Vth. The most popular way of reducing the on-voltage is to reduce the diffusion depth of the p-type well region so that the channel length L may be shortened.
FIG. 12
is a cross sectional view for analyzing the on-voltage components in the IGBT. Referring now to
FIG. 12
, the on-voltage of the IGBT consists of a voltage drop
20
across the channel resistance in a channel region
17
in the surface portion of p-type well region
4
, a parasitic junction FET (JFET) component
21
formed of p-type well regions
4
and
4
on both sides and n-type drift layer
3
, a voltage drop
22
in n-type drift layer
3
, and a voltage drop
23
in p-type collector layer
2
.
The reduction of the on-voltage by reducing the diffusion depth of p-type well region
4
is attributed to the reduction of the voltage drop
20
in channel region
17
and the reduction of the JFET component
21
. Since the load short-circuit current is defined by the foregoing equation (1), the short circuit withstand capability in the short-circuiting of the load is reduced as the short-circuit current is larger.
It is important for the practical power device to exhibit a low on-voltage and a small short-circuit current. However, there exists a close relation between the on-voltage and the short circuit withstand capability. Shortening of the channel length by shallowly diffusing p-type well region
4
causes reduction of the short circuit withstand capability of the device, since the short diffusion depth of p-type well region
4
, that lowers the on-voltage (reduces the loss), increases the short-circuit current.
Thus, it is substantially impossible for the foregoing countermeasures to independently control the channel length and the diffusion depth, i.e. the reduction of the on-voltage and the increase of the short-circuit current by shortening the channel length of the MOSFET and the reduction of the on-voltage by reducing the parasitic JFET component.
In view of the foregoing, i
Fuji Electric & Co., Ltd.
Nguyen Joseph
Rossi & Associates
Wilson Allan R.
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