Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-01-13
2003-11-18
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S369000, C257S379000, C257S531000
Reexamination Certificate
active
06649985
ABSTRACT:
This application is a U.S. National Phase Application under 35 USC 371 of International Application PCT/JP00/04741 filed Jul. 14, 2000.
1. Technical Field
The present invention relates to an insulated-gate semiconductor device suited to be incorporated into a rectifier circuit for performing full-wave rectification of power, which is supplied thereto by inductive coupling through, for example, a coil, to generate internal power.
2. Description of the Related Art
In recent years, there has been proposed a ball semiconductor wherein a functional element such as a transistor, a sensor or the like and a semiconductor integrated circuit or performing certain processing functions are formed on a ball semiconductor chip having a diameter of about 1 mm. As shown in
FIG. 3
, for example, this kind of ball semiconductor includes a ball semiconductor chip
1
and a coil (loop antenna)
2
disposed on the surface of the chip
1
and functioning as an antenna element. This ball semiconductor operates as power, which is generated through inductive coupling at the coil
2
, is supplied from outside. This semiconductor is also constructed to receive and transmit an information signal from and to an external device via the coil.
As shown in
FIG. 4
, an integrated circuit formed on the semiconductor chip
1
includes, for example, a power supply part
3
which receives power (electromagnetic energy) from the external device via the coil
2
to generate an internal power; a receiving circuit
4
for receiving the information signal from the external device via the coil
2
; and a transmitting circuit
5
for transmitting the information signal via the coil
2
to the external device. The integrated circuit further comprises a main circuit
6
including a calculating control part and the like, a sensor circuit
7
such as a temperature sensor, and a memory
8
. This integrated circuit performs a predetermined function as the main circuit
6
operates. Receiving and transmitting the information is carried out through modulation of the information signal, using the electromagnetic induction field for transmitting the power as a carrier.
As shown in
FIG. 5
, the power supply part
3
includes, for example, a rectifier circuit
10
performing full-wave rectification of the power generated through inductive coupling at the coil
2
. The rectifier circuit
10
is constructed in such a way that p-MOS transistors
11
,
12
and n-MOS transistors
13
,
14
, which are all insulated-gate semiconductor devices, are crossed-connected. The rectifier circuit
10
may also be configured such that the p-MOS transistors
11
,
12
are diode-connected, respectively, as shown in FIG.
6
.
As seen from
FIG. 7
illustrating a cross sectional view, the n-MOS transistors
13
,
14
are each constituted in such a way that an n-type source region
22
and a drain region
23
are formed on a p-type semiconductor substrate
21
at a predetermined interval therebetween, and that a gate electrode
25
is formed via an insulating layer
24
over the intermediate area between the source region
22
and the drain region
23
, thereby forming a channel region
26
immediately under the gate electrode
25
. The reference numerals
27
and
28
represent source and drain electrodes formed on the source region
22
and drain region
23
, respectively.
Although not shown, the p-MOS transistors
11
,
12
are constituted in such a way that a p type source region and drain region are formed on the p type semiconductor substrate via an n-well layer and that a channel region is formed immediately under a gate electrode which is formed via an insulating layer over the intermediate area between the source and drain regions.
The source electrode S and drain electrode D of each of the MOS transistors
11
-
14
are generally disposed symmetrical with respect to the gate electrode
25
(G), as shown in
FIG. 8
illustrating a planar electrode pattern. As shown in
FIG. 9
, it is also possible to juxtapose pluralities of MOS transistors and to connect the electrodes S, D and G of the respective MOS transistors, respectively, in parallel to obtain an array configuration, thereby increasing the allowable current capacity.
As shown in
FIG. 10
, the rectifier circuit
10
, which is constituted by the cross-connected MOS transistors
11
,
12
,
13
,
14
as shown in
FIG. 5
, performs full-wave rectification of an input voltage (a dot - dash line A), thus providing a rectified wave as indicated by the dash line B. However, when a smoothing capacitor
15
is connected to the rectifier circuit
10
, it is inevitable that the wave largely decreases in its direct current, as indicated by the thick solid line C in
FIG. 10
, component since the MOS transistors
11
,
12
act as resistance. Specifically, when the input voltage applied to the gate electrode of the p-MOS transistor
11
,
12
becomes lower than the voltage applied to the drain electrode D thereof due to charging of the capacitor
15
, the p-MOS transistor
11
,
12
comes to function as a discharge path for the electric charge stored in the capacitor
15
, since the function of the source is exchanged with that of the drain. Consequently, the output voltage extracted via the capacitor
15
shows a waveform C with a level (voltage) which is nearly an average of the fully rectified voltage waveform B.
On the other hand, with the rectifier circuit
10
constituted by the diode-connected p-MOS transistors
11
,
12
as shown in
FIG. 6
, the input voltage (a dot - dash line A) is fully rectified as denoted by the thin solid line D (in FIG.
10
). The level of the full-wave rectified output obtained in this case is lower than the full-wave rectified output of the waveform B by an amount corresponding to the voltage drop in the p-MOS transistors
11
,
12
functioning as a diode. However, even when the smoothing capacitor
15
is connected to the output side of this rectifier circuit
10
, the p-MOS transistors
11
,
12
do not act as a discharge path for the electric charge stored in the capacitor
15
. This is because the p-MOS transistors
11
,
12
function as a diode. Therefore, the output voltage extracted via the smoothing capacitor has a direct-current component smoothed along an envelope curve, as indicated by the dot - dot - dash line D in FIG.
10
.
However, in order to cause the diodeoconnected p-MOS transistors
11
,
12
of the rectifier circuit
10
to turn on without fail, it is necessary to apply a gate voltage higher than the threshold voltage of the transistors. In this case, however, there is a fear of a parasitic transistor acting due to this gate voltage, causing an undesirable current to flow into the semiconductor substrate
21
.
DISCLOSURE OF THE INVENTION
The present invention was created in view of the above circumstances, and an object thereof is to provide an insulated-gate semiconductor device suited to constitute a rectifier circuit which is capable of obtaining a stable rectified output while restricting a discharge current of a smoothing capacitor, without entailing disadvantages incurred when MOS transistors are diode-connected.
Specifically, the present invention aims at providing an insulated-gate semiconductor device suited to attain a rectifier circuit which can obtain not an average output of full-wave rectified wave but an envelope-curved rectified output thereof even when a smoothing capacitor is incorporated.
Concretely, an insulated-gate semiconductor device of the present invention comprises a source region formed on a semiconductor substrate, a drain region formed on the semiconductor substrate at a distance from the source region, and a gate electrode disposed on the semiconductor substrate with an insulating layer interposed therebetween and forming a channel region between the source region and the drain region, wherein the drain region and the source region are asymmetrical with respect to the channel region.
Preferably, the channel region surrounds the source region, and the drain region is formed around the channel region. Since the drai
Nishimoto Ikuo
Ueno Tatsuya
Frishauf Holtz Goodman & Chick P.C.
Prenty Mark V.
Yamatake Corporation
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