Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1997-10-01
2002-12-31
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S166000, C438S928000
Reexamination Certificate
active
06500703
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an MIS (Metal-Insulator-Semiconductor) device, and particularly, to an MIS transistor. Specifically, the present invention relates to a thin film MIS-type semiconductor device formed on an insulating substrate, and more specifically, to a thin film transistor (TFT). In particular, the present invention relates to a MIS-type semiconductor device of a so-called reversed stagger type comprising a channel forming region on the upper side of a gate electrode. The present invention relates to a semiconductor integrated circuit formed on an insulating substrate, for example, an active matrix circuit and a driver circuit for image sensors.
2. Prior Art
Recently, devices comprising a thin film MIS-type semiconductor device formed on an insulating substrate are brought into practical use. Such a device can be found, for instance, in an active matrix-addressed liquid crystal device. Active matrix circuits commercially available at present include a type using a TFT and a type using a diode such as a MIM. In particular, the active matrix circuits of the former type are fabricated more actively because of the high quality image they yield.
Known active matrix circuits utilizing TFTs include those using polycrystalline semiconductors such as polycrystalline silicon and those using amorphous semiconductors such as amorphous silicon. A TFT using amorphous silicon is referred to hereinafter as an “amorphous silicon TFT”. However, the TFTs of the former type cannot be applied to large area displays because of the process limitations. Accordingly, those of the latter type that are fabricated at a process temperature of 350° C. or lower are mainly used for large area displays.
Referring to
FIGS. 2
(A) to
2
(D), a process for fabricating a prior art amorphous silicon TFT of a reversed stagger type is described below. An alkali-free heat-resistant glass such as a Corning 7059 glass is used for the substrate
201
. Since an amorphous silicon TFT is fabricated by a process with a maximum temperature of about 350° C., materials well resistant to the maximum temperature must be used. In case of using the TFT in a liquid crystal panel, a material having a sufficiently high heat resistance and a high glass transition temperature must be employed to prevent thermal deformation from occurring on the substrate. From this context, Corning 7059 glass is suitable as a substrate material because it undergoes glass transition at a temperature slightly below 600° C.
A TFT capable of stable operation can be realized by excluding mobile ions such as sodium ions from the substrate. The Corning 7059 glass contains very low alkali ions and is therefore ideal from this point of view. If a substrate containing considerable amount of an alkali ion such as sodium ion were to be used, a passivation film made from, for example, silicon nitride or aluminum oxide must be formed on the substrate to prevent mobile ions from intruding into the TFT.
After a coating is formed on the substrate using an electrically conductive material such as an aluminum or tantalum, a tantalum electrode
202
is formed by patterning using a mask
1
. An oxide film
203
is formed on the surface of the gate electrode to prevent short circuit from occurring between the upper wiring and the gate electrode with wiring. The oxide film can be formed mainly by anodic oxidation. In such a case, the oxide film can be formed by applying a positive voltage to the electrode
202
in an electrolytic solution to oxidize the surface of the gate electrode.
A gate dielectric
204
is formed thereafter. In general, silicon nitride is used as the gate dielectric. However, the material for the gate dielectric is not only limited thereto, and it may be silicon oxide or a silicide containing nitrogen and oxygen at a desired ratio. The gate dielectric may be a film of single layer of a multilayered film. A plasma CVD process, for example, can be applied in case silicon nitride film is used as the gate dielectric. The plasma CVD process is effected at a temperature of about 350° C., i.e., the maximum temperature of the present step. The structure thus obtained is shown in
FIG. 2
(A).
An amorphous silicon film is formed thereafter. If the amorphous silicon film is deposited by plasma CVD, the substrate is heated to a temperature in the range of from 250 to 300° C. The film is formed as thin as possible; specifically, it is formed generally at a thickness of from 10 to 100 nm, and preferably, in the range of from 10 to 30 nm. The amorphous silicon film is patterned using a mask {circle around (
2
)} to form an amorphous silicon region
205
. The amorphous silicon region
205
thus formed provides the channel forming region in the later steps. The resulting structure is shown in
FIG. 2
(B).
A silicon nitride film is formed on the entire surface of the resulting structure, and is patterned using a mask {circle around (
3
)} to provide an etching stopper
206
. The etching stopper is provided to prevent accidental etching from occurring on the amorphous silicon region
205
in the channel forming region, because the amorphous silicon region
205
is provided thinly, as mentioned above, at a thickness of from 10 to 100 nm. Moreover, the etching stopper is designed in such a manner that it may be formed superposed on the gate electrode because the amorphous silicon region under the etching stopper functions as the channel forming region. However, misalignment occurs at some extent in the conventional mask alignment. Accordingly, the etching stopper is patterned in such a manner that it may be sufficiently superposed on the gate electrode (i.e., in such a manner that the etching stopper may be smaller than the gate electrode).
An N-type or P-type conductive silicon coating is formed thereafter. In general, an amorphous silicon TFT is of an N-channel type. Since the electric conductivity of an amorphous silicon film thus formed is insufficiently low in conductivity, a microcrystalline silicon film is used alternatively. An N-type conductive microcrystalline silicon film can be fabricated at a temperature of 350° C. or lower by plasma CVD. Still, however, an N-type microcrystalline silicon film must be formed at a thickness of 200 nm or more because the resistance thereof is not sufficiently low. A P-type microcrystalline silicon film has an extremely high resistance and cannot be used as it is. Accordingly, it is difficult to fabricate a P-channel TFT from amorphous silicon.
The silicon film thus fabricated is patterned thereafter using a mask {circle around (
4
)} to provide an N-type microcrystalline silicon region
207
. The resulting structure is shown in
FIG. 2
(C).
The structure of
FIG. 2
(C), however, cannot function as a TFT because the N-type microcrystalline silicon film is joined over the etching stopper. It is therefore necessary to separate the structure at the silicon film joint. Thus, the structure is separated using a mask {circle around (
5
)} to form a trench
208
. If an etching stopper is not provided on the amorphous silicon layer, the base amorphous silicon layer may be accidentally damaged by the etching, because the microcrystalline silicon region
207
is several to several tens of times as thick as the underlying amorphous silicon region, or even thicker.
A wiring
209
and a pixel electrode
210
are formed thereafter by a known process using masks {circle around (
6
)} and {circle around (
7
)}. The state of the resulting structure is shown in
FIG. 2
(D).
In the process above, however, the yield may be lowered because such a large number of masks amounting to 7 are used in the process. Thus, to decrease the number of masks, it is proposed to pattern the gate electrode portion using a first mask on the substrate. Then, a gate dielectric is formed to further deposit continuously thereon an amorphous silicon film and a silicon nitride film to later provide an etching stopper. The structure is exposed thereafter from the back to form an etching stopper in
Booth Richard
Nixon & Peabody LLP
Semicondcutor Energy Laboratory Co., Ltd.
LandOfFree
Insulated gate semiconductor device and process for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Insulated gate semiconductor device and process for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Insulated gate semiconductor device and process for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2994761