Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-28
2001-09-04
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S329000, C438S268000, C438S270000
Reexamination Certificate
active
06285058
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly to an improvement for enhancing a gate breakdown voltage.
BACKGROUND ART
An insulated gate semiconductor device (which will be provisionally referred to as a “vertical device”) including a gate electrode buried in a trench formed in a main surface of a semiconductor substrate, that is, a trench gate has the gate electrode formed in a vertical direction with respect to the main surface differently from an insulated gate semiconductor device (which will be provisionally referred to as a “lateral device”) having a gate electrode formed opposite to the main surface of the semiconductor substrate. Therefore, an area of the main surface occupied by a unit cell can be reduced. Consequently, the number of cells per unit area, that is, a cell density can be increased by using a microfabrication technique.
As the cell density is increased, a main current flowing between a pair of main electrodes of the device when the device is in a conducting state (an ON state) is increased. An electric resistance between a pair of main electrodes which is obtained when the insulated gate semiconductor device is in the conducting state is referred to as an “ON-state resistance”, and is one of important indices to evaluate the characteristic of the device. In the lateral device, when the cell density is increased to exceed a certain limit, a “j-FET resistance” which is one of components of the ON-state resistance is considerably increased. For this reason, the lateral device has a limit to increase the main current while keeping the ON-state resistance within a certain range.
On the other hand, the vertical device has an advantage that there is no limit derived from the j-FET resistance. As a typical example making the most of the advantage of the vertical device, a MOSFET (MOS field effect transistor) having a trench gate and an IGBT (Insulated Gate Bipolar Transistor) having a trench gate have widely been known.
FIG. 69
is a plan view showing a gate wiring region of a MOSFET having a trench gate according to the prior art. Moreover,
FIGS. 70 and 71
are sectional views taken along cutting lines A—A and B—B in
FIG. 69
, respectively. In a device
150
, an n-type epitaxial layer
72
is formed on an n-type substrate layer
71
including an n-type impurity having a high concentration and has a lower impurity concentration than in the n-type substrate layer
71
. By these semiconductor layers, a semiconductor substrate
99
is constituted.
A p-type semiconductor layer
96
and a p well layer
73
are selectively formed in a surface of the n-type epitaxial layer
72
, that is, an upper main surface of the semiconductor substrate
99
. The p well layer
73
is formed to be connected to the p-type semiconductor layer
96
, and furthermore, to surround a periphery of the p-type semiconductor layer
96
.
A plurality of gate trenches
76
arranged in parallel with each other are formed like a band in the upper main surface of the semiconductor substrate
99
. The gate trench
76
is formed more deeply than the p-type semiconductor layer
96
and more shallowly than the n-type epitaxial layer
72
. In the gate wiring region shown in
FIGS. 69
to
71
, an edge of the gate trench
76
along its longitudinal direction is present. An internal wall of the gate trench
76
is covered with a gate insulating film
78
. A gate electrode
77
made of polysilicon doped with an impurity having a high concentration is buried in the gate trench
76
through the gate insulating film
78
.
In the gate wiring region, an area in the upper main surface of the semiconductor substrate
99
where a gate electrode
7
is not present is covered with an insulating film
87
or an insulating film
74
. The insulating film
74
is selectively formed as a LOCOS (local oxidation of silicon) film more thickly than the insulating film
87
in a direction of an array of gate trenches
6
over the p well layer
73
while keeping a space with the gate trench
6
. In the vicinity of an end of the gate trench
6
along its longitudinal direction, the gate electrode
77
is connected to a gate wiring
79
.
The gate wiring
79
is formed of the same material as a material of the gate electrode
77
, and furthermore, is continuously provided integrally with the gate electrode
77
. Moreover, the gate wiring
79
is provided on the insulating film
74
and is extended toward the gate trench
6
to cover an edge portion of the gate electrode
77
in order to implement a connection with the gate electrode
77
. The insulating film
74
is provided to keep a high breakdown voltage between the gate wiring
79
and the p well layer
73
.
Furthermore, an n-type semiconductor layer
75
containing arsenic in a high concentration is selectively formed in the upper main surface of the semiconductor substrate
99
. The n-type semiconductor layer
75
is formed to surround an upper end UE of an edge of the gate trench
6
along its longitudinal direction. In a process of manufacturing the device, the n-type semiconductor layer
75
is formed, and the gate trench
76
and the insulating film
87
are then formed by a thermal oxidation treatment. At this time, the oxidation is accelerated by the action of the impurity contained in the n-type semiconductor layer
75
. Therefore, the gate trench
76
and the insulating film
87
which cover the vicinity of the upper end UE are completed thickly. Consequently, it is possible to obtain the effect of increasing insulation strengths of the gate electrode
77
and the insulating film
87
in the vicinity of the upper end UE.
The surfaces of the gate electrode
77
and the gate wiring
79
are covered with an insulator having a three-layer structure constituted by an insulating film
86
, a BPSG layer
81
and an insulating film
89
. Both of the insulating films
86
and
89
are made of oxide. A source electrode
84
and a gate wiring
83
are provided on the insulating film
89
. Both the source electrode
84
and the gate wiring
83
are made of Al—Si. In the insulator having the three-layer structure, an opening
95
is selectively formed in a portion provided above the insulating film
74
, and the gate wiring
79
and the gate wiring
83
are electrically connected through the opening
95
. A drain electrode
85
is provided on a lower main surface of the semiconductor substrate
99
, that is, a surface of the n-type substrate layer
71
.
An n-type source layer is selectively formed in an area in the upper main surface of the semiconductor substrate
99
which is provided adjacently to the gate trench
76
over the cell region of the device, which is not shown. The source electrode
84
is connected to the n-type epitaxial layer
72
and the n-type source layer which are exposed to the upper main surface of the semiconductor substrate
99
in the cell region. A portion of the p-type semiconductor layer
96
which is interposed between the n-type source layer and the n-type epitaxial layer
72
and is opposed to the gate electrode
77
functions as a channel region.
When using the device, a positive voltage with reference to the source electrode
84
is applied to the drain electrode
85
. By regulating a voltage to be applied to the gate electrode
77
through the gate wiring
83
and the gate wiring
79
, a magnitude of the main current flowing from the drain electrode
85
to the source electrode
84
is controlled.
In order to make the drain electrode
85
and the source electrode
84
conductive, a positive gate voltage for the source electrode
84
is applied to the gate electrode
77
. Since the gate electrode
77
and the gate wiring
79
are connected to each other, their electric potentials are equal to each other. Moreover, since the p well layer
73
and the source electrode
14
are connected to each other, their electric potentials are also equal to each other. For this reason, when the device is set in a conducting state, an electric field E having
Narazaki Atsushi
Souno Hidetoshi
Yamashita Yasunori
Mitsubishi Denki & Kabushiki Kaisha
Niebling John F.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Simkovic Viktor
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