Insulated gate semiconductor device

Details Insulated gate semiconductor device Insulated gate semiconductor device

2001-04-26

2004-05-18

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S331000, C257S139000, C257S341000, C257S152000

Reexamination Certificate

active

06737705

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to insulated gate semiconductor devices such as insulated gate bipolar transistors (hereinafter referred to as “IGBT's”).
BACKGROUND
To reduce the electric power consumption of the electric power conversion apparatuses, it is necessary to reduce the electric power consumption of the semiconductor power devices, which are the main constituent elements of the electric power conversion apparatuses. Among the semiconductor power devices, IGBT's have been widely used since the IGBT's facilitate realizing low on-resistance by conductivity modulation and are easily driven by controlling the gate potential thereof. The IGBT's may be classified into a planar IGBT and a trench-type IGBT. The planar IGBT includes gate electrodes on the semiconductor chip surface. The trench-type IGBT includes trenches dug from the semiconductor chip surface and gate electrodes buried in the trenches. Since channels are formed on both sides of each trench, the channel density in the trench-type IGBT is high. The trench-type IGBT has been used more widely than the planar IGBT, since the trench-type IGBT facilitates in further reducing the on-resistance due to the high channel density thereof.
FIG. 9
is a cross sectional view of a conventional trench-type and n-channel IGBT perpendicular to the extending direction of the trench gates thereof. Referring now to
FIG. 9
, the conventional trench-type and n-channel IGBT includes a heavily doped p-type silicon substrate
1
; a lightly doped n-type drift layer
2
on silicon substrate
1
; a p-type base layer
3
on n-type drift layer
2
; and n
+
-type source regions
4
formed selectively in the surface portion of p-type base layer
3
. Trenches are formed from the surfaces of n
+
-type source regions
4
down to n-type drift layer
2
through p-type base layer
3
. A polycrystalline silicon gate electrode
6
, working as a control electrode, is buried in each trench with a gate oxide film
5
interposed therebetween. An interlayer insulation film
7
is on gate electrode
6
such that interlayer insulation film
7
covers the upper end of gate electrode
6
. An emitter electrode
8
on interlayer insulation films
7
contacts commonly with p-type base layer
3
and n
+
-type source regions
4
. Although not illustrated in
FIG. 9
, a passivation film such as a silicon nitride film or an amorphous silicon film is sometimes on emitter electrode
8
. A collector electrode
9
is on the back surface of p-type silicon substrate
1
.
Now the operation for bringing the conventional trench-type and n-channel IGBT into the ON-state thereof will be explained below. Usually, emitter electrode
8
is connected to the ground. The IGBT is in the OFF-state thereof when the voltage applied to collector electrode
9
is higher than the ground potential and the voltage applied to gate electrodes
6
is lower than the threshold value. When a voltage higher than the threshold value is applied to gate electrodes
6
, a gate drive circuit
10
starts accumulating electric charges on gate electrodes
6
via gate resistance
11
. At the same time, the portions of p-type base layer
3
facing to gate electrodes
6
through respective gate oxide films
5
are inverted to n-type, resulting in channel portions. Electrons are injected from emitter electrode
8
into n-type drift layer
2
via n
+
-type source regions
4
and the resulting channel portions in p-type base layer
3
. Since the injected electrons apply a forward bias voltage between p-type silicon substrate
1
and n-type drift layer
2
, holes are injected from collector electrode
9
. The voltage drop caused between emitter electrode
8
and collector electrode
9
at this moment is the on-state voltage drop of the IGBT.
By lowering the voltage between emitter electrode
8
and gate electrodes
6
below the threshold value, the IGBT is brought into an OFF-state from the ON-state thereof. As the voltage between emitter electrode
8
and gate electrodes
6
is lowered below the threshold value, the electric charges accumulated on gate electrodes
6
are discharged to gate drive circuit
10
via gate resistance
11
. In association with the discharge, the channel portions, which have been converted to n-type, return to p-type. Since there are no channels left any longer, neither electrons nor holes are injected any more. The accumulated electrons are swept out to collector electrode
9
. The accumulated holes are swept out to emitter electrode
8
. Or, the excess electrons and holes recombine to vanish. As a result, the IGBT is brought into the OFF-state thereof.
Various improvements have been proposed to further reduce the on-voltage of the IGBT's. Japanese Unexamined Laid Open Patent Application H05-243561 discloses an injection enhanced gate bipolar transistor (hereinafter referred to as an “IEGT”), that exhibits an on-voltage as low as the on-voltage of the diode. In the IEGT, some n
+
-type source regions and some regions of the p-type base layer are covered with an insulation film so that these regions may not contact with the emitter electrode. Although the IEGT works basically in the same way as the trench-type IGBT, the holes below the regions of the p-type base layer, including the n
+
-type source regions, which are not in direct contact with the emitter electrode, are hardly swept out to the emitter electrode. Since the holes, not swept out to the emitter electrode, are accumulated, the distribution of the carriers below the regions of the p-type base layer not in direct contact with the emitter electrode is close to that in the diode. As a result, the on-voltage of the IEGT is lower than the on-voltage of the conventional trench-type IGBT. However, it is required for the semiconductor power devices to exhibit high-speed switching characteristics in addition to a low on-voltage. Therefore, it is also important to improve the switching characteristics of the trench-type IGBT.
Since the trench-type IGBT and the IEGT include trenches formed at a high density as described above, large capacitance is caused between the gate electrodes and the emitter electrode thereof. As described in connection with the operations of the IGBT, it is necessary to electrify or discharge the above-described capacitance during the transition from the OFF-state to the ON-state or vice versa. When the capacitance is large, the time for electrifying or discharging is prolonged. This delay for electrifying or discharging further causes an increase in loss. The losses caused in the semiconductor power device are the sum of the steady state loss determined by the on-voltage and the switching loss caused by the turn-on and turn-off of the device. Therefore, it is important to reduce the switching loss; that is, to reduce the capacitance between the gate electrodes and the emitter electrode.
In view of the foregoing, it would be desirable to provide a trench-type IGBT, that obviates the problems described above. It would further be desirable to provide a trench-type IGBT that facilitates reducing the total losses by lowering the switching loss while suppressing the on-voltage thereof as low as the on-voltage of the IEGT.
SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided an insulated gate semiconductor device including: a first semiconductor layer of a first conductivity type having a first major surface and a second major surface; a lightly doped second semiconductor layer of a second conductivity type on the first major surface of the first semiconductor layer; a third semiconductor layer of the first conductivity type on the second semiconductor layer, the third semiconductor layer being doped more heavily than the second semiconductor layer, the third semiconductor layer being formed of first regions and second regions arranged alternately; fourth semiconductor layers of the second conductivity type formed selectively in the surface portions of the first regions of the third semiconductor layer; trenche

Affiliated with

Also associated with

Rating

Insulated gate semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Insulated gate semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Insulated gate semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3271246