Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-15
2001-10-09
Trinh, Michael (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S392000, C257S406000
Reexamination Certificate
active
06300663
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to insulated-gate field-effect transistors and more particularly to such transistors formed on a single substrate and having different gate capacitances.
2. Description of the Related Art
In some circumstances, for example, static random access memory (SRAM) implemented with insulated-gate field-effect transistors (IGFETs), it is desirable to form IGFETs on a single semiconductor substrate with some having substantially larger gate capacitances than others. An SRAM cell implemented with IGFETs typically includes a bistable circuit in the form of a cross-coupled flip-flop. A pair of gating transistors couple storage transistors in the cell to different bit lines. The gating transistors are turned on and off to read the state of the cell, i.e., to apply a high or low voltage to the associated bit line. When one of the gating transistors is turned on, charge flows from the storage transistor and, if sufficient flow occurs, thereby change the state of the cell. It is obviously undesirable for the cell state to change when the state is read. To prevent such unintended state changes, the storage FET in the cell is typically made 4-5 times larger than that of the gating FET. A storage transistor having a substantially larger area, and therefore a substantially larger capacitance, prevents substantial charge flow during a read operation thereby preventing an unintended state change in the cell responsive to the read operation.
Utilizing transistors which are 4-5 times larger than other transistors on the substrate is disadvantageous, however, because it takes up area on the semiconductor substrate and thereby limits the number of devices which can be formed on the substrate.
It would be desirable to provide IGFETs formed on a single substrate and having different gate capacitances which utilize less area than such prior art IGFETs.
SUMMARY OF THE INVENTION
An integrated circuit formed on a single substrate comprises a first FET formed on the substrate and having a first area and a first capacitance. A second FET formed on the substrate has an area substantially equal to the first area with a capacitance substantially less than the first capacitance. In one aspect, one of the FETs has a substantially thicker gate oxide than the other FET. In another aspect, the gate oxide of one of the FETs is formed from a different material than that of the other FET.
A method for fabricating such IGFETs on a single substrate is also provided in which source and drain regions are formed adjacent the surface of the substrate. A first layer of gate oxide is formed on the surface of the substrate over the channels of the first and the second FETs. The first layer of gate oxide is then covered by a nitride layer which is thereafter etched away over the channel of one of the FETs. A second layer of gate oxide is deposited on the first layer of gate oxide exposed as a result of the etching. Thereafter, the nitride layer and that portion of the first layer of gate oxide not over the channel of either FET are both removed.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment which proceeds with reference to the drawings.
REFERENCES:
patent: 3837071 (1974-09-01), Ronen
patent: 4003071 (1977-01-01), Takagi
patent: 4257832 (1981-03-01), Schwabe et al.
patent: 5057449 (1991-10-01), Lowrey et al.
patent: 5480828 (1996-01-01), Hsu et al.
patent: 5521117 (1996-05-01), Kapoor
patent: 5918116 (1999-06-01), Chittipeddi
LSI Logic Corporation
Trinh Michael
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