Insulated-gate field-effect transistor, method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S063000, C257S616000

Reexamination Certificate

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06936875

ABSTRACT:
With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.

REFERENCES:
patent: 6403981 (2002-06-01), Yu
patent: 6475869 (2002-11-01), Yu
patent: 6563152 (2003-05-01), Roberds et al.
patent: 9-321307 (1997-12-01), None
patent: 2000-286418 (2000-10-01), None
patent: 2002-16255 (2002-01-01), None
patent: 2003-17710 (2003-01-01), None
Hisamoto et al., “A Folded-channel MOSFET for Deep-sub-tenth Micron Era,” Proceedings of the International Electronic Device Conference (IEDM) , 1988, pp. 1032-1034.

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