Insulated gate field effect transistor having vertically layered

Details Insulated gate field effect transistor having vertically layered Insulated gate field effect transistor having vertically layered

1991-06-27

1993-08-10

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257382, H01L 2976

Patent

active

052352030

ABSTRACT:
An insulated gate field effect transistor having a vertically layered elevated source/drain structure includes an electrically conductive suppression region for resistance to hot carrier injection. The device includes a semiconductor substrate of first conductivity type having a gate insulator disposed on the surface of that substrate. A gate electrode, in turn, is disposed on the gate insulator. A lightly doped drain region of second conductivity type is formed in the substrate in alignment with the gate electrode. An electrically conductive suppression region having a first low electrical conductivity is positioned to electrically contact the drain region, but is electrically isolated from the gate electrode and is spaced a first distance from the gate electrode. A heavily doped drain contact also contacts the drain region and is spaced further away from the gate electrode than is the electrically conducted suppression region.

REFERENCES:
patent: 4948745 (1990-08-01), Pfiester et al.
patent: 5068696 (1991-11-01), Yang et al.
patent: 5102816 (1992-04-01), Manukonda et al.
Semiconductor Devices-Physics and Technology, p. 376, S. M. Sze, 1985.

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