Insulated gate field effect transistor and semiconductor...

Details Insulated gate field effect transistor and semiconductor... Insulated gate field effect transistor and semiconductor...

2001-04-09

2003-12-02

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S343000, C257S347000, C257S348000, C257S350000, C257S351000, C257S354000, C257S368000, C257S369000, C257S492000, C438S149000, C438S479000, C438S517000

Reexamination Certificate

active

06657257

ABSTRACT:

BACKGROUND OF THE INVENTION
In a conventional technology of an insulated gate field effect transistor, if the insulated gate field effect transistor is arranged to have an avalanche breakdown, i.e., an element withstand voltage when no voltage is applied to the gate electrode thereof, of more than 30 V, the following construction is employed. That is, for example, if the insulated gate field effect transistor is an N-type channel lateral MOS field effect transistor formed as an N-type substrate, as shown in
FIG. 2
, a silicon oxide film
12
is formed on an Si substrate
13
of N-type or P-type, an N-type Si substrate
11
is formed on the silicon oxide film
12
, a source electrode
15
is provided on the N-type Si substrate, a high concentration N-type layer
61
and a high concentration P-type layer
71
are formed so as to contact to the source electrode
15
, a combination of a gate oxide film
32
and a gate electrode
31
is provided so as to contact to the high concentration N-type layer
61
, and a P-type region (p-body layer)
41
is formed so as to contact to the gate oxide film
32
, the high concentration N-type layer
61
and the high concentration P-type layer
71
. Further, a drain electrode
16
is provided at a lateral position with respect to the combination of the gate oxide film
32
and the gate electrode
31
through a field oxide film
21
contacting to the combination, and a high concentration N-type layer
62
is provided so as to contact to the drain electrode
16
.
Conversely, if the insulated gate field effect transistor is formed as a P-type substrate, as shown in
FIG. 3
, the silicon oxide film
12
is formed on the Si substrate
13
of the N-type or P-type, a P-type Si substrate
19
is formed on the silicon oxide film
12
, a source electrode
15
is provided on the P-type Si substrate
19
, and the high concentration N-type layer
61
and the high concentration P-type layer
71
are formed so as to contact to the source electrode
15
, the combination of the gate oxide film
32
and the gate electrode
31
is provided so as to contact to the high concentration N-type layer
61
, and the P-type region (p-body layer)
41
is formed so as to contact to the gate oxide film
32
, the high concentration N-type layer
61
and the high concentration P-type layer
71
. Further, the drain electrode
16
is provided at a lateral position with respect to the combination of the gate oxide film
32
and the gate electrode
31
through the field oxide film
21
contacting to the combination, and the high concentration N-type layer
62
is provided so as to contact to the drain electrode
16
. Furthermore, the P-type substrate
19
has an N-type region
101
formed so that the N-type region
101
is contacted to the gate oxide film
32
, and extends to be contacted to the high concentration N-type layer
62
contacting to the drain electrode
16
.
However, it is often requested that a so-called MOS field effect transistor can afford a withstand voltage, or the avalanche breakdown exceeding the rated voltage thereof, even if the MOS field effect transistor is placed in an on-state, e.g., the MOS field effect transistor is applied at its gate electrode with a voltage which exceeds the threshold voltage thereof. (The withstand voltage when the MOS field effect transistor is placed in the on-state is hereinafter referred to as on-breakdown.) However, if the N-type channel lateral MOS field effect transistor using the N-type substrate is fabricated as shown in
FIG. 2
based on the conventional technology, on-breakdown exceeding the rated value cannot be guaranteed unless a sufficient distance is provided between the source electrode and the drain electrode. On the other hand, if the lateral size of the device is made large, the drain resistance also becomes large, with the result that the MOS field effect transistor suffers from deterioration in the on-resistance. This is undesirable matter for the MOS field effect transistor.
On the other hand, if the N-type channel lateral MOS field effect transistor is arranged as one employing the P-type substrate, it is allowable to make the on-breakdown greater than the rated value without increasing the distance between the source electrode and the drain electrode. However, in order to realize the N-type channel lateral MOS field effect transistor using the P-type substrate, it is indispensable to form a PN-junction between the P-type substrate and the N-type region
101
of the N-type channel lateral MOS field effect transistor. Which fact makes it difficult to fabricate a thin film transistor having an Si layer as the SOI substrate serving as a device formation area. The thickness of the Si layer of the SOI (Silicon On Insulator) substrate serving as the device formation area is deeply concerned with a problem of a time for forming a trench as a separation wall in a semiconductor device. That is, as the thickness of the Si layer becomes large, it takes a long time to form the trench, leading to lower throughput. Therefore, it is disadvantageous in terms of cost performance. Conversely, if any thin film technology is established for making thin the Si layer, which serves as the device formation area of the SOI substrate, then the following advantages can be expected. That is, it becomes allowable to bury a source region or a drain region in the Si substrate of a low-voltage CMOS device, which is driven at a low voltages such as 5 V, 3.3 V, 2.5 V to bring them into contact with an oxide film, together with any device having a high withstand voltage. In this way, since a parasitic capacitance of the source region and the drain region can be eliminated, it is expected to improve the performance of the CMOS device driven at a low voltage. However, if the device employs the P-type substrate, it will be difficult to improve the performance of the CMOS device driven at a low voltage.
Further, an N-type channel MOS field effect transistor using Si substrate, not SOI substrate, is widely utilized. However, if such device is utilized in a power IC which is often provided with a high withstand voltage device mounted thereon, a sufficient distance shall be required between each of the devices for avoiding undesirable operation in the transistor due to parasitic capacitance. Further, the above-described device has a relatively large leak current at a high temperature operation as compared with that of the device using the SOI substrate.
SUMMARY OF THE INVENTION
The present invention is made in view of the above aspect. Therefore, it is an object of the present invention to provide an insulated gate field effect transistor employing an SOI substrate in which it is possible to improve the on-breakdown of the transistor without increasing the size of the device.
According to an N-type insulated gate field effect transistor using an N-type SOI substrate as an Si layer serving as a device formation area of present invention, the SOI substrate is arranged to have an N-type semiconductor region (n-body layer), which has an impurity concentration higher than the impurity concentration of the N-type Si layer serving as the device formation area of the SOI substrate, so that the N-type semiconductor region is contacted to a part of the gate oxide film and the field silicon oxide film formed between the source electrode and the drain electrode and extends to be contacted to an N-type diffusion layer contacted to the drain electrode. With this arrangement, the on-breakdown will be remarkably improved.
Initially, conditions influential in determining the on-breakdown will be described. The on-breakdown is a withstand voltage at which current is abruptly flowed from a saturation region in a chart descriptive of a drain voltage to drain current characteristic when a MOS field effect transistor having an N-type channel formed therein is applied with a positive voltage at its gate electrode and hence the MOS field effect transistor is placed in an on-state. When a channel is formed, electrons are flowed from the source region through the channel re

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