Insulated gate field effect transistor and a method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE29158

Reexamination Certificate

active

07977751

ABSTRACT:
Disclosed herein is an insulated gate field effect transistor including: (A) a source/drain region and a channel formation region; (B) a gate electrode formed above the channel formation region; and (C) a gate insulating film; wherein the gate insulating film is composed of a gate insulating film main body portion formed between the gate electrode and the channel formation region, and a gate insulating film extension portion extending from the insulating film main body portion to a middle of a side surface portion of the gate electrode, and when a height of the gate electrode is HGateand a height of the gate insulating film extension portion is HInswith a surface of the channel formation region as a reference, a relationship of HIns<HGateis fulfilled.

REFERENCES:
patent: 6448163 (2002-09-01), Holbrook et al.
patent: 2002/0153537 (2002-10-01), Segawa
patent: 2003/0003666 (2003-01-01), Iriyama et al.
patent: 11-243150 (1999-09-01), None
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patent: 2001-085677 (2001-03-01), None
patent: 2001-127288 (2001-05-01), None
patent: 2001-274380 (2001-10-01), None
patent: 2005-136366 (2005-05-01), None
patent: 01/71807 (2001-09-01), None
Atsushi Yagishita et al.; High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1um Regime; International Electron Devices Meeting 1998; Technical Digest pp. 785-788 (1988).
Japanese Office Action issued on May 7, 2009 corresponding to JP Application No. 2007-132364.

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