Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-15
2001-07-10
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000
Reexamination Certificate
active
06259141
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an insulated gate field effect semiconductor device using a thin film semiconductor (hereinafter referred to as a TFT) and a method for forming the insulated gate field effect semiconductor device, and particularly to a gate electrode and a method for forming the gate electrode.
2. Description of Related Art
A self-alignment type of structure has been known as a conventional TFT structure. In this structure, impurity material which provides one conductivity type is doped by an ion implantation method or the like using a gate electrode portion as a mask to form source/drain regions.
FIGS. 1A and 1B
show a representative structure of this self-alignment structure of a TFT. In
FIG. 1A
, the structure includes an insulating substrate
21
of glass or the like, a thin film semiconductor layer
22
in which a source region
25
, a channel forming region
27
and a drain region
26
are formed, a gate insulating film
23
and a gate electrode
24
. Also, electrodes, layer insulating films, wirings, etc. which are well known but are not shown in
FIG. 1A
, are also formed in this structure.
In
FIG. 1A
, the semiconductor layer
22
is formed of amorphous silicon or crystallized amorphous silicon. The source region
25
and the drain region
26
are doped with phosphorus to form N-type regions. Accordingly, the TFT as shown in
FIG. 1A
is an N-channel type TFT. The gate insulating film
23
is formed of silicon oxide (SiO
2
), and the gate electrode
24
is formed of a silicon film which is doped with a large amount of phosphorus in order to reduce the resistance of the gate electrode
24
.
The TFT shown in
FIG. 1A
is formed as follows. The amorphous silicon semiconductor layer
22
is first formed on the substrate
21
by a vapor phase method. Thereafter, the amorphous silicon semiconductor layer
22
is heated or irradiated with a laser beam in order to crystallize it, whereby the amorphous silicon semiconductor layer is transformed to crystallized silicon.
Subsequently, an oxidized silicon film serving as the gate insulating film
23
is formed by a sputtering method or the like and a silicon film doped with phosphorus, serving as the gate electrode
24
, is formed by a vapor phase method or the like. Thereafter the gate insulating film
23
and the gate electrode
24
are formed in a patterning process to obtain an intermediate product having the shape shown in FIG.
1
A. Subsequently, implantation (introduction) of phosphorus ions (hereinafter referred to as “ion implantation”) is performed using the gate electrode
24
as a mask to form the source region
25
and the drain region
26
in a self-alignment structure. In this case, the channel forming region
27
is automatically formed.
Thereafter, through heat treatment, activation of the introduced phosphorus impurity and scratch of the semiconductor layer
22
in the ion implantation process are annealed. In this heat treatment, the gate electrode
24
formed of amorphous silicon is crystallized.
In this case, the following problem occurs.
In the heat treatment after the ion implantation process, the phosphorus diffuses from the gate electrode
24
and penetrates through the gate insulating film
23
to the channel forming region
27
, as indicated by arrows
28
of
FIG. 1B
, so that the channel forming region
27
becomes an N-type region. As a result, the channel forming region does not function effectively, and the characteristic of the TFT deteriorates.
In order to solve the above problem, the following methods (a) to (d) may be adopted:
(a) Adoption of a doping method which requires no heat treatment,
(b) Lowering the heat treatment temperature and shortening the heat treatment time,
(c) Lowering the concentration of introduced phosphorus ions into the gate electrode
24
, and
(d) Use of a metal material requiring no ion implantation for the gate electrode.
The method (a) is not realistic because the doping system itself must be altered. That is, those devices and forming methods which are presently used cannot be utilized.
The method (b) cannot obtain various effects, such as the improvement of interface characteristics at the interface between the channel forming region
27
and the gate insulating film
23
which are obtained by heat treatment, the restoration of damage of the semiconductor layer
22
which occurs in the ion implantation process, etc., and thus does not basically solve the problem. In practical use, as a compromise, a heat treatment condition is set in a suitable permissible range in consideration of the treatment temperature and treatment time in the heat treatment process and the degree of diffusion of the impurities into the channel forming region.
The method (c) necessarily causes the resistance of the gate electrode to be increased, and this causes an increase in wiring resistance and cannot obtain the characteristics of the TFT.
In the method (d), the heat tolerance temperature of the metal material of the gate electrode
24
is an important factor in the heat treatment process after ion implantation and a subsequent protection film forming process. Therefore, the heat treatment temperature is restricted. Further, there is a problem in that although the gate electrode is not melted, the metal material of the gate electrode
24
diffuses into the channel forming region
27
.
The above problems occur similarly for both N-channel type Tats and P-channel type TFTS, and are not dependent on elements introduced by ion implantation. cl SUMMARY OF THE INVENTION
An object of the present invention is to provide a TFT structure and a forming method thereof in which introduced ions are prevented from penetrating through a gate insulating film
23
and diffusing into a channel forming region
27
in a heat treatment process after ion implantation during manufacture of a TFT having a self-alignment structure as shown in FIG.
1
A.
In order to attain the above object, according to a first aspect of the present invention, an insulated gate field effect semiconductor device is characterized in that the concentration of impurities which provides one conductivity type in a gate electrode formed of a semiconductor material is set to be low in one region of the gate electrode which is in contact with a gate insulating film, and set to be high in the other region.
According to the first aspect of the present invention, the concentration of impurities which provides one conductivity type in the gate electrode is set to be low at one side of the gate electrode which is in contact with the gate insulating film, and set to be high at the opposite side of the gate electrode to the gate insulating film. Therefore, the amount of impurities which penetrate from the gate electrode through the gate insulating film in a TFT forming process can be reduced. The following structure can be provided to realize a structure according to the first aspect of the invention.
In the following description, the construction of each part of
FIG. 2
is the same as the construction shown in
FIG. 1A
, except for the structure of the gate electrode
24
.
In the structure of the TFT as shown in
FIG. 2
, the gate electrode
24
formed of the semiconductor layer is so designed that the impurity providing one conductivity type is contained at a low concentration at one side
31
of the gate electrode
24
which is in contact with the gate insulating film
23
, and in high concentration at the other (opposite) side
32
of the gate electrode
24
which is not in contact with the gate insulating film
23
.
The structure of TFT as shown in
FIG. 2
may be realized by a method wherein the impurity which provides one conductivity type is gradually doped into the gate electrode
24
from starting of film formation of the gate electrode
24
in accordance with the progress of the film formation of the gate electrode
24
, or by a method wherein the gate electrode is made a multi-layered structure and the respective layers of the multi-layered structure are successively f
Ngo Ngan V.
Nixon & Peabody LLP
Robinson Eric J.
Semiconductor Energy Labortary Co., Ltd.
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