Insulated gate field effect semiconductor device

Details Insulated gate field effect semiconductor device Insulated gate field effect semiconductor device

2001-07-30

2003-06-10

Wille, Douglas A. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S331000

Reexamination Certificate

active

06576955

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an insulated gate field effect semiconductor device, and more particularly, to an insulated gate field effect semiconductor device that reduces the on-state resistance to improve the stability of the potential of the substrate thereby reducing the leakage current between drain and source regions.
BACKGROUND OF THE INVENTION
With the widespread use of mobile terminals, requirements for small-size, large-capacity lithium-ion batteries have increased. The protection circuit to implement battery management for charging and discharging lithium-ion batteries must be small in size and strong enough to withstand possible short circuit of load to meet the need of light-weight design of mobile terminals. Such protection circuit needs to be mounted in the container of the lithium-ion battery; therefore, small-size design is expected and the COB (Chip On Board) technology using many chips has been employed to meet small-size requirements.
On the other hand, however, power MOSFET's are connected in series with the lithium-ion battery; therefore, there is a need for minimizing the on-state resistance of the power MOSFET. This is an indispensable ingredient for elongating the calling period or standby period in the mobile telephone applications. In order to reduce the on-state resistance, it is necessary to get more current paths. For that purpose, high integration of cells by reducing the cell pitch through the use of micro-fabrication technology and widening the channel width per unit area are expected as major technologies.
FIG.
4
and
FIG. 5
show a top view of a trench type power MOSFET based on conventional wiring pattern.
In
FIG. 4
, a top view of a MOSFET with trenches
27
formed in lattice structure is shown. The trench type MOSFET is composed of lattice type trenches
27
, the gate electrode
32
which is embedded inside the trench
27
, the source region
33
which is provided along the trench
27
, and the body contact region
35
which is provided in the region surrounded by the source region
33
. Here, interlayer insulating film and source electrode are omitted.
The portion given in broken line is the cell
38
, one of the cells of trench type MOSFET.
The trench
27
is about 1 &mgr;m in width and is formed in lattice structure spaced at about 5 &mgr;m on the actual operating region and the inside wall is covered with a gate oxide layer (not shown).
The gate electrode
32
is designed to have a low resistance by introducing an impurity while embedding polysilicon inside the trench
27
.
The source region
33
is provided along the trench
27
and is formed in the shape of square or the equivalent shape. This allows the width of channel region per unit area (channel width) which may become a current path to be increased and thus the on-state resistance to be reduced.
The body contact region
35
is formed in island configuration surrounded by source region
33
in the shape of square with sides of about 2 &mgr;m or in the equivalent shape for the stabilization of the potential of the substrate.
The channel region (not shown) is formed in the direction from the source region
33
to the depth of the trench
27
and adjacent to the gate electrode
32
with a gate oxide layer (not shown) between them.
FIG. 5
shows a top view of the MOSFET that has trenches
27
formed in stripes. Since the trenches
27
are formed in stripes spaced at about 5 &mgr;m and the source regions
33
provided along trenches
27
also take the form of stripes, the source regions
33
are continuous among a plurality of cells
38
. The body contact region
35
is formed like an island at about the center portion of the source region
33
and adjacent to the source region
33
.
Accordingly, even if the body contact region
35
is poor in contact in one cell
38
, the potential of the substrate is kept stable because the channel region (not shown) is continuous unlike the lattice structure.
In
FIG. 6
, the structure of the power MOSFET of conventional trench structure is shown taking an N-channel type as an example.
The drain region
22
consisting of the N
−
-type epitaxial layer on the N
+
-type silicon semiconductor substrate
21
and the channel layer
24
of P type on the surface of the region. The trench
27
through the channel layer
24
and reaches the drain region
22
is provided and the gate electrode
32
that is comprised of the inside wall of a trench
27
covered with a gate oxide layer
28
and polysilicon filling trench
27
is provided.
On the surface of the channel layer
24
adjacent to the trench
27
is formed the N
+
-type source region
33
and on the surface of the channel layer
24
between the source regions
33
of two adjacent cells
38
is provided the P
+
-type body contact region
35
. In addition, on the channel layer
24
is formed the channel region
34
along the source region
33
through the trench
27
.
The gate electrode
32
is covered with the interlayer insulator
36
and the source electrode
37
to contact the source region
33
and the body contact region
35
is provided.
A conventional trench has the following problems in its shape.
First, with the pattern configuring trench in lattice structure, a cell
38
is surrounded by some trenches
27
like an island and the body contact region
35
is formed in a minute area to attain highly integrated configuration. Accordingly, silicon nodule that is mixed when sputtering source electrode
37
may block the body contact region
35
and the electric charge of the channel region
34
induced by the gate electrode
32
may lose its escape way.
In other words, the potential of the channel region
34
fluctuates in a single cell
38
in island, showing the same state as that a voltage is always being applied by the gate electrode
32
, and thereby results in the state the channel is open. As a result, current leaks from the cell and may be considered as the cause of leakage current between the drain and source regions.
On the other hand, with the pattern of forming the trenches
27
in stripes, even if the body contact region
35
becomes poor in contact in a single cell
38
, the channel region
34
is continuous among a plurality of cells
38
. Therefore, without being affected by the silicon nodule, the potential of the substrate is kept more stable than the case with the trench
27
formed in lattice structure. As a result, it is considered that no leakage current may occur between the drain and source regions.
With the pattern formed in stripes, however, as the spacing between trenches
27
is designed to meet the size (about 2 &mgr;m in width) of body contact region
35
, the number of channel regions
34
per unit area may not be increased as compared with the trench in lattice structure. Accordingly, the on-state resistance is less advantageous than the case with a form of lattice structure and is not suited for low on-state resistance implementation.
SUMMARY OF THE INVENTION
The present invention is made for solving the above-mentioned problems of conventional techniques. An object of the invention is to provide the method of improving the stability of potential in the substrate even when poor contact is present in the body contact region, thus preventing leakage current and attaining the low on-state resistance implementation.
In order to attain the above object, according to the first aspect of this invention, there is provided an insulated gate field effect semiconductor device having, a semiconductor substrate with a drain region formed in it and a plurality of trenches provided on a surface of the substrate. Trenches are formed as stripes aligning in a direction. The device also has a gate electrode embedded inside the trench, a gate insulating film provided on an inside wall of the trench for covering the gate electrode, and a source region provided on the substrate surface adjacent to the trench. In this configuration, the strips of the trench are deformed so that a portion of the surface of the substrate defined by t

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