Insulated gate bipolar transistor, semiconductor device,...

Details Insulated gate bipolar transistor, semiconductor device,... Insulated gate bipolar transistor, semiconductor device,...

2002-09-27

2004-05-11

Tsai, H. Jey (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S138000, C257S142000, C257S342000, C438S328000

Reexamination Certificate

active

06734497

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an insulated gate bipolar transistor, a manufacturing method of such a transistor, a semiconductor device using such an insulated gate bipolar transistor and a manufacturing method thereof.
BACKGROUND ART
In a power semiconductor device for driving a load such as a motor, an insulated gate bipolar transistor (referred to simply as an IGBT) is used in a rated voltage area of not less than 300 V as a switching element installed therein so as to provide a better characteristic. In this case, a circulating diode parallel-connected to the switching element is used at the same time.
FIG. 29
is a front cross-sectional view that shows a conventional IGBT. This IGBT
151
comprises a semiconductor substrate
90
having first and second major surfaces. This semiconductor substrate
90
, which is a silicon substrate, comprises a P
+
collector layer
91
that is a P
+
substrate exposed to the first major surface, an N
+
buffer layer
92
formed thereon, an N
−
base layer
93
that is formed thereon, and has a lower concentration of impurities than the N
+
buffer layer
92
, a P base region
2
that is formed by selectively diffusing P-type impurities on the second major surface to which the N
−
base layer
93
is exposed, and an N
+
source region
3
that is formed as a shallower region than the P base region
2
by selectively diffusing N-type impurities with a high concentration inside this P base region
2
.
On the second major surface of the semiconductor substrate
90
is formed a gate insulating film
4
made of a silicon dioxide in a manner so as to cover one portion of a surface of P the base region
2
and a surface of the N
−
base layer
93
. A gate electrode
5
made of polysilicon is formed on the gate insulating film
4
. On the upper major surface of the semiconductor substrate
90
, an emitter electrode
7
is further formed so as to connect one portion of the surface of the N
+
source region
3
and a center area of the surface of the P base region
2
. The gate electrode
5
and the emitter electrode
7
are insulated from each other by an interlayer insulating film
6
.
Therefore, the N
−
base layer
93
, the P base region
2
and the N
+
source region
3
, which are formed on the second major surface side of the semiconductor substrate
90
, correspond to a semiconductor portion of an MOS transistor. The portion having the same structure as the MOS transistor, which is formed on the second major surface of the semiconductor substrate
90
, is referred to as an MOS structure M. A portion of the surface of the P base region
2
, which is located right below the gate electrode
5
, and sandwiched by the source region
3
and the N
−
base layer
93
, that is, a portion at which the gate electrodes
5
face each other with the gate insulating film
4
sandwiched in between, corresponds to a channel region CH of the MOS structure M. The P base region
2
and the N
+
source region
3
are formed by selectively implanting and diffusing impurities by using the gate electrode
5
as a mask. That is, since the P base region
2
and the N
+
source region
3
form a double diffusion region, the MOS structure M forms one example of a Double Diffused MOS (referred to simply as a DMOS). A collector electrode
8
to be connected to the P
+
collector layer
91
is formed on the first major surface of the semiconductor substrate
90
.
FIG. 30
is a front cross-sectional view of an insulated gate bipolar transistor in accordance with another conventional example. This IGBT
151
a
is typically different from IGBT
151
in its MOS structure M formed on the second major surface side of the semiconductor substrate
90
. A trench
9
, which penetrates an N
+
source region
3
and a P base region
2
to reach an N
−
base layer
93
, is formed on the second major surface, and a gate insulating film
4
is formed in a manner so as to cover the inner wall face thereof. Moreover, a gate electrode
5
is buried inside the gate insulating film
4
. In this IGBT
151
a
also, a portion of a surface of the P base region
2
(which includes a surface exposed to the trench
9
), which is sandwiched by the N
+
source region
3
and an N
−
base layer
93
, that is, a portion at which the gate electrodes
5
face each other with the gate insulating film
4
sandwiched in between, corresponds to a channel region CH of an MOS transistor.
In this manner, each of the planar IGBT
151
of FIG.
29
and the trench-type IGBT
151
a
of
FIG. 30
comprises the P
+
collector layer
91
that is exposed to the first major surface of the semiconductor substrate
90
, the N base layers
92
,
93
formed thereon, the MOS structure M (including one portion of the N
−
base layer
93
) formed on the second major surface and the collector electrode
8
that is formed on the first major surface and connected to the P
+
collector layer
91
. Normally, a number of cells, shown in
FIGS. 29 and 30
, are reciprocally arranged along the major surfaces of the semiconductor substrate
90
so that a greater current rate is obtained by this arrangement. In
FIG. 29
, one cell is drawn, and in
FIG. 30
, two cells are drawn.
Next, the operations of IGBT
151
and
151
a
will be described. In the structures of
FIGS. 29 and 30
, with a predetermined collector-emitter voltage (referred to as a collector voltage) V
CE
being applied between the emitter electrode
7
and the collector electrode
8
, a gate-emitter voltage (referred to as a gate voltage) V
GE
with a positive bias having a predetermined level is applied between the emitter electrode
7
and the gate electrode
5
; that is, upon turning on the gate, the conductive type of the channel region CH is inverted from a P type to an N type. As a result, a channel serving as a carrier path is formed in the channel region CH. Electrons are injected from the emitter electrode
7
to the N
−
base layer through this channel. The electrons thus injected make the P
+
collector layer
91
and the N base layers
92
,
93
forwardly biased so that holes are injected to the N base layers
92
,
93
from the P
+
collector layer
91
. As a result, the resistance of the N
−
base layer
92
drops greatly so that the current capacity of the IGBT
151
,
151
a
is increased.
Next, when the gate voltage V
GE
is set from a positive bias value to 0 or a reverse bias value, that is, when the gate is turned off, the channel region CH, inverted to the N type, is restored to the P type. Consequently, the injection of electrons from the emitter electrode
7
is stopped. The stop of injection of electrons also stops the injection of holes from the P
+
collector layer
91
. Thereafter, electrons and holes, accumulated in the N base layers
92
,
93
, are either drawn into the collector electrode
8
and the emitter electrode
7
, respectively, or recombined with each other to disappear.
Next, a description will be given of a semiconductor device as a typical applied apparatus of the conventional IGBTs
151
and
151
a
.
FIG. 31
is a circuit diagram (in which
151
is typically added as a reference number for an IGBT) of a semiconductor device using the IGBTs
151
,
151
a
as switching elements. This semiconductor device
152
is formed as a three-phase inverter. Freewheel diodes
160
are parallel-connected to six IGBTs
151
, respectively. Freewheel diodes
160
are connected in such a direction that the reverse current of the corresponding IGBT
151
is bypassed. The parallel connection in this direction is also referred to as “reverse parallel connection”.
With respect to six IGBTs
151
, every two of them are series-connected. The collector electrode
8
of one of two series-connected IGBTs
151
is connected to a higher potential power-supply terminal PP, and the emitter electrode
7
of the other is connected to a lower potential power-supply terminal NN. That is, three series circuits, each

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