Instructions for efficiently accessing unaligned vectors

Electrical computers and digital processing systems: processing – Instruction alignment

Reexamination Certificate

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Details

C712S223000, C712S225000, C712S226000, C712S005000

Reexamination Certificate

active

07620797

ABSTRACT:
One embodiment of the present invention provides a processor which is configured to execute load-swapped instructions, which are possibly directed to unaligned source address. The processor is configured to execute the load-swapped instruction by loading a vector from a naturally-aligned memory region encompassing the source address, and in doing so rotating the bytes of the vector to cause the byte at the specified source address to reside at the least-significant byte position within the vector for a little-endian memory transaction, or causing said byte to be positioned at the most-significant byte position within the vector for a big-endian memory transaction. In a variation on this embodiment, the processor is also configured to execute a store-swapped instruction directed to a destination address by storing a vector into a naturally-aligned memory region encompassing the destination address, and in doing so rotating the bytes of the vector to cause the least significant byte of the vector to be stored to at the specified destination address on a little-endian processor, or causing the most significant byte of the vector to be stored to the destination address said on a big-endian processor, or causing the specified byte to be stored to the destination address in the case of an endian-specific store-swapped variant.

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