Instruction set reconciliation for heterogeneous...

Details Instruction set reconciliation for heterogeneous... Instruction set reconciliation for heterogeneous...

2006-07-18

2006-07-18

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C713S002000, C713S500000, C712S216000, C712S226000

Reexamination Certificate

active

07080242

ABSTRACT:
In a symmetric multiprocessing system using processors (DP0–DP7) of different capabilities (instruction sets), a processor responds (S11) to a query regarding its capabilities (instruction set) with its “active” capability, which is the intersection of its native capability and a common capability across processors determined (S04) during a boot sequence (13). The querying application (29) can select (S12) a program variant optimized for the active capability of the selected processor. If the application is subsequently subjected to a blind transfer to another processor, it is more likely than it would otherwise be (if the processors responded with their native capabilities) that the previously selected program variant runs without encountering unimplemented instructions.

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patent: 2004/0088460 (2004-05-01), Poisner
patent: 2005/0166214 (2005-07-01), Kaulgud et al.

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