Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-28
2005-06-28
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06912706
ABSTRACT:
A method and arrangement for executing instructions of a computer program using a programmable logic device to perform selected functions of the program. Profile data for code segments of the computer program are generated during program execution. Based on the profile data, a code segment is selected for transformation to a hardware implementation. The functionality of the selected code segment is transformed into a configuration bitstream, and the PLD is configured with the configuration bitstream. During program execution, the PLD is activated in lieu of executing the code segment.
REFERENCES:
patent: 5109353 (1992-04-01), Sample et al.
patent: 5499192 (1996-03-01), Knapp et al.
patent: 5684980 (1997-11-01), Casselman
patent: 5802290 (1998-09-01), Casselman
patent: 5946219 (1999-08-01), Mason et al.
patent: 6023755 (2000-02-01), Casselman
patent: 6077315 (2000-06-01), Greenbaum et al.
patent: 6078736 (2000-06-01), Guccione
patent: 6216259 (2001-04-01), Guccione et al.
patent: 6289440 (2001-09-01), Casselman
patent: 6430736 (2002-08-01), Levi et al.
patent: 6438738 (2002-08-01), Elayda
patent: 6496971 (2002-12-01), Lesea et al.
patent: 645 723 (1995-03-01), None
patent: WO 94/10627 (1994-05-01), None
Xilinx, Inc.; “The Programmable Logic Data Book”; Sep. 1996; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 4-251 to 4-286.
Eric Lechner and Steven A. Guccione; “The Java Environment for Reconfigurable Computing”; Proceedings—Field Programmable Logic and Applications, 7th International Workshop, FPL 1997; London, UK; Sep. 1-3, 1997, pp. 284-293.
Iseli et al.; “A C + + Compiler for FPGA Custom Execution Units Synthesis”; Apr. 19-21, 1995; IEEE Symposium on FPGAs for Custom Computing Machines; pp. 173-179.
Peterson et al.; “Scheduling and Partitioning ANSI-C Programs Onto Multi-FPGA CCM Architectures”; IEEE Symposium on FPGAs for Custom Computing Machines; Apr. 17-19, 1996; pp. 178-187.
Guccione et al.; “A Data-Parallel Programming Model for Reconfigurable Architectures”; Apr. 5-7, 1993; IEEE Workshop on FPGAs for Custom Computing Machines; pp. 79-87.
McGloin Ciaran
McNicholl David
Stamm Reto
Cartier Lois D.
Maunu LeRoy D.
Smith Matthew
Tat Binh
Xilinx , Inc.
LandOfFree
Instruction processor and programmable logic device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Instruction processor and programmable logic device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Instruction processor and programmable logic device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3521795