Instruction processing apparatus using a microprogram that...

Details Instruction processing apparatus using a microprogram that... Instruction processing apparatus using a microprogram that...

1999-12-16

2004-06-22

Wiley, David (Department: 2143)

Electrical computers and digital processing systems: processing

Processing control

Processing sequence control

Reexamination Certificate

active

06754814

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an instruction processing apparatus in an information processing system.
2. Description of the Related Art
In an information processing system, when a load control (LCTL) instruction or other instruction requiring serial processing, a load program status word (LPSW) instruction or other instruction for changing the controlled state of a system, or an interrupt is executed, instructions have to be re-read.
Recent information processing systems use a microprogram so as to execute instructions while reducing the hardware. Similar use is made of a microprogram for realizing a method for re-reading instructions due to execution of an LCTL instruction or other instruction requiring serial processing, a LPSW instruction or other instruction for changing the controlled state of a system, or an interrupt.
FIG. 1
is a flowchart of the routine for an instruction re-read operation using a microprogram.
An instruction re-read operation using a microprogram is realized by, in time, starting up the microprogram (step S
1
), halting the reading of instructions (step S
2
), setting an instruction read address (step S
3
), and starting the reading of instructions (step S
4
).
A conventional instruction processing unit adopting pipeline processing performs similar processing to that of FIG.
1
.
A conventional instruction re-read method using pipeline processing will be described next using
FIG. 2
to FIG.
13
.
FIG. 2
to
FIG. 5
show an instruction processing circuit.
FIG. 2
shows the overall configuration of the circuit and the connection of
FIG. 3
to FIG.
5
.
FIG. 6
to
FIG. 8
are timing charts of instruction re-re-read processing.
FIG. 9
to
FIG. 13
show the hardware configuration employed in the instruction processing circuit.
A basic instruction re-read operation description follows.
The basic instruction re-read processing is performed by an LPSW instruction. Among the timing charts of
FIG. 6
to
FIG. 8
,
FIG. 6
shows the processing of this example.
The routine of
FIG. 1
in an LPSW instruction as executed as follows. First, in the startup of the microprogram of step S
1
of
FIG. 1
, instructions fetched into an instruction buffer (IBUFFER) of
FIG. 3
are loaded into an instruction register (IWR), the instructions are decoded at the D-cycle, and an operation code (IO) is supplied to a control storage address register (CSAR). By this, microprogram control information (PLHC, PCR, LAST-WORD, etc.) is successively read from a main control storage (MCS) into a D-tag (DTAG). The PLHC is a Pipeline Hardware Control used for interlock controlling of the pipeline, the PCR is a Program Control Register mainly used for controlling REGISTER, and the LAST-WORD (Last-Word) contains data read from the MCS, which shows the end of the microprogram. The microprogram control information is shifted from the D-cycle to a W-Cycle for the processing at the cycles (D-Cycle to W-Cycle).
The halting of the reading of instructions at step S
2
of
FIG. 1
is performed by a function counter
2
(FC
2
) of FIG.
6
. Microprogram control information (PLHC=0C) of the FC
2
read from the MCS of
FIG. 3
is shifted from the D-cycle to the W-cycle. At this time, the microprogram control information (PLHC=0C) from the TTAG of the T-cycle is decoded and a T-CONTROL signal (A) is produced (see
FIG. 10
) and sent to an instruction reading control unit of FIG.
3
. For explanation, a function counter (e.g. FC
2
, shown in
FIG. 6
) indicates a count of a series of processes from D-cycle to W-cycle. The function counters FC
0
-FCn are not constituted by hardware, but are indications that show function units processed by the data read from the MCS in each fetch cycle.
The sent T-CONTROL signal (A) activates the RE-IFCH-TGR of FIG.
12
and halts the reading of instructions by a signal (C): +IF-REQ signal sent from the instruction reading control unit of
FIG. 3
(see FIG.
12
). At the same time, the instruction buffer is initialized by clearing the NSI-COUNTER of
FIG. 3
showing the state of the IBUFFER and the location of instructions by a signal (D): −INITIALIZE-NSIC signal (see
FIG. 12
) sent from the instruction reading control unit.
The setting of the instruction read address of step S
3
in
FIG. 1
is performed by a function counter FC
0
of FIG.
6
. The microprogram control information (PCR=14) of the FC
0
read from the MCS of
FIG. 3
is shifted from the D-cycle to the W-cycle. At this time, an operand fetch instruction is issued by an A-CONTROL signal of the A-cycle of
FIG. 4
, microprogram control information (PCR=14) is decoded from the WTAG of the W-cycle of
FIG. 5
, a W-CONTROL signal (E) is produced (see FIG.
11
), the result register latch (RR-LCH) of
FIG. 5
is selected, and the output is written in a program status word (PSW).
Next, at the W+1 cycle of
FIG. 5
, an instruction address (PSWIAR) of the PSW updated by a W-CONTROL-LCH signal (F) latching the W-CONTROL signal (E) of
FIG. 11
is loaded into an instruction address register (IAR).
The starting of reading of instructions of step S
4
of
FIG. 1
is performed by FC
5
of FIG.
6
. Microprogram control information (LAST-WORD) of the FC
5
read from the MCS of
FIG. 3
is shifted from the D-cycle to the W-cycle. At this time, the AND of the microprogram control information (LAST-WORD) and a D-VALID signal (signal indicating that the D-cycle is valid) is taken from the DTAG of the D-cycle of
FIG. 3
, whereby an NSI-REQ signal (G) is produced and sent to the instruction reading control unit of FIG.
3
.
The NSI-REQ signal (G) sent to the instruction reading control unit of
FIG. 3
resets the latch of RE-IFCH-TRG of FIG.
12
and then activates the latch of START-UP, whereby an IF-REQ signal (C) is sent from the next clock cycle and thereby instructions start being read.
By the processing of the microprogram as explained above, the routine of
FIG. 1
is satisfied and the basic instruction re-read operation indicated in
FIG. 6
is carried out.
An example of producing subsequent instruction address and performing instruction re-read operation follows. The instruction re-read operation at the subsequent instruction address is performed by the load control (LCTL) instruction. Among the timing charts of
FIG. 6
to
FIG. 8
,
FIG. 7
shows the processing of this example.
The LCTL also performs the instruction re-read operation according to the routine of FIG.
1
. The startup of the microprogram for the instruction re-read operation of step S
1
, the halting of reading of instructions of step S
2
, and the starting of reading of instructions of step S
4
in this example are similar to those of the above explanation of the basic instruction re-reading operation. Only the setting of the instruction read address of step S
3
differs.
In the same way as the above basic instruction re-reading operation, a microprogram is started up at step S
1
and the halting of the reading of instructions of step S
2
is performed by the FC
2
of FIG.
7
.
The setting of the instruction read address of step S
3
of
FIG. 1
is performed by the FC
6
of FIG.
7
. In the same way as the microprogram control information (PLHC=0F) of the FC
6
read from the MCS of
FIG. 3
being shifted from the D-cycle to the W-cycle, an address in the IAR corrected by an instruction address modifier (IAM) sent from the instruction reading control unit of FIG.
3
and an instruction length code decoded from the IWR are shifted.
At this time, microprogram control information (PLHC=0F) is decoded from the TTAG of the T-cycle, a T-CONTROL signal (B) is produced (see FIG.
10
), TIAR+TILC obtained by adding the data of the T-cycle instruction address register (TIAR) and the T-cycle of
FIG. 4
instruction length code (TILC) is selected, and the TIAR+TILC is loaded into the IAR.
Next, for the start of the reading of instructions of step S
4
of
FIG. 1
, processing similar to that explained in the above basic instruct

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