Instruction length decoder

Details Instruction length decoder Instruction length decoder

2007-12-04

2007-12-04

Kindred, Alford (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction alignment

C712S210000, C712S024000, C712S212000, C712S213000

Reexamination Certificate

active

10180389

ABSTRACT:
Speculatively decoding instruction lengths in order to increase instruction throughput. Instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor clock cycles.

REFERENCES:
patent: 5535347 (1996-07-01), Grochowski et al.
patent: 5537629 (1996-07-01), Brown et al.
patent: 6237074 (2001-05-01), Phillips et al.
patent: 6260134 (2001-07-01), Zuraski et al.
patent: 6405303 (2002-06-01), Miller et al.

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