Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition
Reexamination Certificate
1999-08-11
2001-01-09
Vu, Viet D. (Department: 2758)
Electrical computers and digital processing systems: processing
Processing control
Instruction modification based on condition
C712S221000, C712S224000, C708S525000
Reexamination Certificate
active
06173394
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application relates to improvements in the inventions disclosed in the following copending U.S. patent applications, all of which are assigned to Texas Instruments:
U.S. patent application Ser. No. 08/263,504 filed Jun. 21, 1994, now U.S. Pat. No. 5,471,592 issued Nov. 28, 1995 and entitled “MULTI-PROCESSOR WITH CROSSBAR LINK OF PROCESSORS AND MEMORIES AND METHOD OF OPERATION”; which is a continuation of U.S. patent application Ser. No. 08/135,754 filed Oct. 12, 1993, now abandoned; which is a continuation of U.S. patent application Ser. No. 07/933,865 filed Aug. 21, 1992, now abandoned; which is a continuation of U.S. patent application Ser. No. 07/435,591 filed Nov. 17, 1989, now abandoned.
U.S. patent application Ser. No. 07/437,858 filed Nov. 17, 1989, now U.S. Pat. No. 5,212,777 issued May 18, 1993 and entitled “MULTI-PROCESSOR RECONFIGURABLE IN SINGLE INSTRUCTION MULTIPLE DATA (SIMD) AND MULTIPLE INSTRUCTION MULTIPLE DATA (MIMD) MODES AND METHOD OF OPERATION”.
U.S. patent application Ser. No. 08/264,111 filed Jun. 22, 1994, now U.S. Pat. No. 5,522,083 issued May 28, 1996 and entitled “RECONFIGURABLE MULTI-PROCESSOR OPERATING IN SIMD MODE WITH ONE PROCESSOR FETCHING INSTRUCTIONS FOR USE BY REMAINING PROCESSORS”; which is a continuation of U.S. patent application Ser. No. 07/895,565 filed Jun. 5, 1992, now abandoned; which is a continuation of U.S. patent application Ser. No. 07/437,856 filed Nov. 17, 1989, now abandoned.
U.S. patent application Ser. No. 08/264,582 filed Jun. 22, 1994 now pending and entitled “REDUCED AREA OF CROSSBAR AND METHOD OF OPERATION”; which is a continuation of U.S. patent application Ser. No. 07/437,852 filed Nov. 17, 1989, now abandoned.
U.S. patent application Ser. No. 08/032,530 filed Mar. 15, 1993 now pending and entitled “SYNCHRONIZED MIMD MULTI-PROCESSING SYSTEM AND METHOD”; which is a continuation of U.S. patent application Ser. No. 07/437,853 filed Nov. 17, 1989, now abandoned.
U.S. patent application Ser. No. 07/437,946 filed Nov. 17, 1989, now U.S. Pat. No. 5,197,140 issued Mar. 23, 1993 and entitled SLICED ADDRESSING MULTI-PROCESSOR AND METHOD OF OPERATION.
U.S. patent application Ser. No. 07/437,857 filed Nov. 17, 1989, now U.S. Pat. No. 5,339,447 issued Aug. 16, 1994 and entitled ONES COUNTING CIRCUIT, UTILIZING A MATRIX OF INTERCONNECTED HALF-ADDERS, FOR COUNTING THE NUMBER OF ONES IN A BINARY STRING OF IMAGE DATA.
U.S. patent application Ser. No. 07/437,851 filed Nov. 17, 1989, now U.S. Pat. No. 5,239,654 issued Aug. 24, 1993 and entitled DUAL MODE SIMD/MIMD PROCESSOR PROVIDING REUSE OF MIMD INSTRUCTION MEMORIES AS DATA MEMORIES WHEN OPERATING IN SIMD MODE.
U.S. patent application Ser. No. 07/911,562 filed Jun. 29, 1992, now U.S. Pat. No. 5,410,649 issued Apr. 25, 1995 and entitled “IMAGING COMPUTER AND METHOD OF OPERATION”; which is a continuation of U.S. patent application Ser. No. 07/437,854 filed Nov. 17, 1989, now abandoned.
U.S. patent application Ser. No. 07/437,875 filed Nov. 17, 1989, now U.S. Pat. No. 5,226,125 issued Jul. 6, 1993 and entitled “SWITCH MATRIX HAVING INTEGRATED CROSSPOINT LOGIC AND METHOD OF OPERATION”.
This application is also related to the following concurrently filed U.S. patent applications, which include the same disclosure:
U.S. patent application Ser. No. 08/486,562 filed Jun. 7, 1995 now U.S. Pat. No. 5,696,954 issued Dec. 9, 1997 entitled “THREE INPUT ARITHMETIC LOGIC UNIT WITH BARREL ROTATOR”, a continuation of U.S. patent application Ser. No. 08/160,299 filed Nov. 30, 1993;
U.S. patent application Ser. No. 08/158,742 now U.S. Pat. No. 5,640,578 issued Jun. 17, 1997 entitled “ARITHMETIC LOGIC UNIT HAVING PLURAL INDEPENDENT SECTIONS AND REGISTER STORING RESULTANT INDICATOR BIT FROM EVERY SECTION”;
U.S. patent application Ser. No. 08/478,129 filed Jun. 7, 1995 now U.S. Pat. No. 5,696,959 issued Dec. 9, 1997 entitled “MEMORY STORE FROM A REGISTER PAIR CONDITIONAL”, which is a continuation of U.S. patent application Ser. No. 08/160,118 now abandoned;
U.S. patent application Ser. No. 08/324,323 filed Oct. 17, 1994 now U.S. Pat. No. 5,442,581 issued Aug. 15, 1995 entitled “ITERATIVE DIVISION APPARATUS, SYSTEM AND METHOD FORMING PLURAL QUOTIENT BITS PER ITERATION”, which is a continuation of U.S. patent application Ser. No. 08/160,115 now abandoned;
U.S. patent application Ser. No. 08/159,285 now U.S. Pat. No. 5,596,763 issued Jan. 21, 1997 entitled “THREE INPUT ARITHMETIC LOGIC UNIT FORMING MIXED ARITHMETIC AND BOOLEAN COMBINATIONS”;
U.S. patent application Ser. No. 08/473,380 filed Jun. 7, 1995 now U.S. Pat. No. 5,727,225 issued Mar. 10. 1998 entitled “METHOD, APPARATUS AND SYSTEM FORMING THE SUM OF DATA IN PLURAL EQUAL SECTIONS OF A SINGLE DATA WORD”, which is a continuation of U.S. patent application Ser. No. 08/160,119;
U.S. patent application Ser. No. 08/159,359 now U.S. Pat. No. 5,512,896 issued Apr. 30, 1996 entitled “HUFFMAN ENCODING METHOD, CIRCUITS AND SYSTEM EMPLOYING MOST SIGNIFICANT BIT CHANGE FOR SIZE DETECTION”;
U.S. patent application Ser. No. 08/160,296 now U.S. Pat. No. 5,479,166 issued Dec. 26, 1995 entitled “HUFFMAN DECODING METHOD, CIRCUIT AND SYSTEM EMPLOYING CONDITIONAL SUBTRACTION FOR CONVERSION OF NEGATIVE NUMBERS”;
U.S. patent application Ser. No. 08/160,112 entitled “METHOD, APPARATUS AND SYSTEM FOR SUM OF PLURAL ABSOLUTE DIFFERENCES”;
U.S. patent application Ser. No. 08/160,120 now U.S. Pat. No. 5,644,524 issued Jul. 1, 1997 entitled “ITERATIVE DIVISION APPARATUS, SYSTEM AND METHOD EMPLOYING LEFT MOST ONE'S DETECTION AND LEFT MOST ONE'S DETECTION WITH EXCLUSIVE OR”;
U.S. patent application Ser. No. 08/160,114 now U.S. Pat. No. 5,712,999 issued Jan. 27, 1998 entitled “ADDRESS GENERATOR EMPLOYING SELECTIVE MERGE OF TWO INDEPENDENT ADDRESSES”;
U.S. patent application Ser. No. 08/160,116 now U.S. Pat. No. 5,420,809 issued May 30, 1995 entitled “METHOD, APPARATUS AND SYSTEM METHOD FOR CORRELATION”;
U.S. patent application Ser. No. 08/160,297 now U.S. Pat. No. 5,509,129 issued Apr. 16, 1996 entitled “LONG INSTRUCTION WORD CONTROLLING PLURAL INDEPENDENT PROCESSOR OPERATIONS”;
U.S. patent application Ser. No. 08/159,346 now U.S. Pat. No. 6,067,613 issued May 23, 2000 entitled “ROTATION REGISTER FOR ORTHOGONAL DATA TRANSFORMATION”;
U.S. patent application Ser. No. 08/159,652 entitled “MEDIAN FILTER METHOD, CIRCUIT AND SYSTEM”;
U.S. patent application Ser. No. 08/159,344 now U.S. Pat. No. 5,805,913 issued Sep. 8, 1998 entitled “ARITHMETIC LOGIC UNIT WITH CONDITIONAL REGISTER SOURCE SELECTION”;
U.S. patent application Ser. No. 08/160,301 entitled “APPARATUS, SYSTEM AND METHOD FOR DIVISION BY ITERATION”
U.S. patent application Ser. No. 08/159,650 now U.S. Pat. No. 5,644,522 issued Jul. 1, 1997 entitled “MULTIPLY ROUNDING USING REDUNDANT CODED MULTIPLY RESULT”;
U.S. patent application Ser. No. 08/159,349 now U.S. Pat. No. 5,446,651 issued Aug. 29, 1995 entitled “SPLIT MULTIPLY OPERATION”;
U.S. patent application Ser. No. 08/482,697 filed Jun. 7, 1995 now U.S. Pat. No. 5,689,695 issued Nov. 18, 1997 entitled “MIXED CONDITION TEST CONDITIONAL OPERATIONS AND CONDITIONAL BRANCH OPERATIONS”, which is a continuation of U.S. patent application Ser. No. 08/158,741 now abandoned;
U.S. patent application Ser. No. 08/472,828 filed Jun. 7, 1995 U.S. Pat. No. 5,606,677 issued Feb. 25, 1997 entitled “PACKED WORD PAIR MULTIPLY OPERATION”, which is a continuation of U.S. patent application Ser. No. 08/160,302 now abandoned;
U.S. patent application Ser. No. 08/160,573 now U.S. Pat. No. 6,098,163 issued Aug. 1, 2000 entitled “THREE INPUT ARITHMETIC LOGIC UNIT WITH SHIFTER
U.S. patent application Ser. No. 08/159,282 now U.S. Pat. No. 5,590,350 issued Dec. 31, 1996 entitled “THREE INPUT ARITHMETIC LOGIC UNIT WITH MASK GENERATOR”;
U.S. patent application Ser. No. 08/475,134 now U.S. Pat. No. 5,634,065 issued May 27, 1997 entitled “THREE INPUT ARITHMETIC LOGIC UNIT WITH BARREL ROTATOR AND MASK GENERATOR”, which is a continuation of U.S. patent application Ser. No. 08/160,111;
U.S. patent application Ser. No. 08/160,298 now U.S. Pat. No. 5,974,539 issued
Balmer Keith
Guttag Karl M.
Poland Sydney W.
Brady III W. James
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Vu Viet D.
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