Instruction fetch mechanism with simultaneous prediction of cont

Details Instruction fetch mechanism with simultaneous prediction of cont Instruction fetch mechanism with simultaneous prediction of cont

1997-06-19

1999-10-12

Treat, Wiiliam M.

Electrical computers and digital processing systems: processing

Processing control

Branching

712240, G06F 938

Patent

active

059648694

ABSTRACT:
A microprocessor is provided with an instruction fetch mechanism that simultaneously predicts multiple control-flow instructions. The instruction fetch unit further is capable of handling multiple types of control-flow instructions. The instruction fetch unit uses predecode data and branch prediction data to select the next instruction fetch bundle address. If a branch misprediction is detected, a corrected branch target address is selected as the next fetch bundle address. If no branch misprediction occurs and the current fetch bundle includes a taken control-flow instruction, then the next fetch bundle address is selected based on the type of control-flow instruction detected. If the first taken control-flow instruction is a return instruction, a return address from the return address stack is selected as the next fetch bundle address. If the first taken control-flow instruction is an unconditional branch or predicted taken conditional branch, a predicted branch target address is selected as the next fetch bundle address. If no branch misprediction is detected and the current fetch bundle does not include a taking control-flow instruction, then a sequential address is selected as the next fetch bundle address.

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