Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
2011-06-07
2011-06-07
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S216000
Reexamination Certificate
active
07958338
ABSTRACT:
An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.
REFERENCES:
patent: 5778243 (1998-07-01), Aipperspach et al.
patent: 5802339 (1998-09-01), Sowadsky et al.
patent: 5872963 (1999-02-01), Bitar et al.
patent: 7509511 (2009-03-01), Barowski et al.
patent: 2002/0095614 (2002-07-01), Rodgers et al.
patent: 2004/0073781 (2004-04-01), Hokenek et al.
patent: 2006/0020776 (2006-01-01), Yoshida
patent: 2006/0026594 (2006-02-01), Yoshida et al.
patent: 2006/0161421 (2006-07-01), Kissell
patent: 2007/0067612 (2007-03-01), Kan et al.
patent: 2008/0040589 (2008-02-01), Sakamoto et al.
patent: 1622000 (2006-02-01), None
patent: 3646137 (2005-05-01), None
patent: 2006-502504 (2006-01-01), None
patent: 2006-39815 (2006-02-01), None
patent: 2006-40141 (2006-02-01), None
patent: 2007-87108 (2007-04-01), None
patent: 2007-109057 (2007-04-01), None
patent: 2004/034209 (2004-04-01), None
patent: WO-2004/034340 (2004-04-01), None
patent: WO-2006/114874 (2006-11-01), None
International Search Report for PCT/JP2007/000652, mailed Sep. 4, 2007.
Extended European Search Report dated Dec. 7, 2010 for corresponding European Application No. 07790178.3.
Akizuki Yasunobu
Kan Ryuji
Tanaka Tomohiro
Yoshida Toshio
Fujitsu Limited
Fujitsu Patent Center
Pan Daniel
LandOfFree
Instruction execution control device and instruction... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Instruction execution control device and instruction..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Instruction execution control device and instruction... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2708466