Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
2007-10-02
2007-10-02
Sparks, Donald (Department: 2181)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S215000, C712S216000, C712S217000, C712S218000
Reexamination Certificate
active
10331917
ABSTRACT:
An instruction execution apparatus comprising a register storing a copy of contents of a maximum number of entries that are executable simultaneously in one cycle with the entry storing the oldest unreleased instruction at a head among all entries in an instruction storage device after execution of the instructions, a completion condition determination section44for determining whether the instructions stored in the entries of the register are completed in the cycle for determining completion conditions of the entries in the instruction storage device, and an entry release section44for releasing only the entries that are determined to be completed by the completion condition determination section among all entries in the instruction storage device, which allows the entries in the CSE to be released smoothly even though the number of entries in a commitment stack entry, or clock frequency, is increased.
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Akizuki Yasunobu
Inoue Aiichiro
Fujitsu Limited
Moll Jesse R.
Sparks Donald
Staas & Halsey , LLP
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