Electrical computers and digital processing systems: processing – Processing control – Mode switch or change
Reexamination Certificate
2011-03-08
2011-03-08
Li, Aimee J (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Mode switch or change
C712S043000, C712S228000
Reexamination Certificate
active
07904704
ABSTRACT:
A system, apparatus and method for instruction dispatch on a multi-thread processing device are described herein. The instruction dispatching method includes, in an instruction execution period having a plurality of execution cycles, successively fetching and issuing an instruction for each of a plurality of instruction execution threads according to an allocation of execution cycles of the instruction execution period among the plurality of instruction execution threads. Remaining execution cycles are subsequently used to successively fetch and issue another instruction for each of the plurality of instruction execution threads having at least one remaining allocated execution cycle of the instruction execution period. Other embodiments may be described and claimed.
REFERENCES:
patent: 5964843 (1999-10-01), Eisler et al.
patent: 5966543 (1999-10-01), Hartner et al.
patent: 7212155 (2007-05-01), Hatch et al.
patent: 7334086 (2008-02-01), Hass et al.
patent: 7340742 (2008-03-01), Tabuchi
patent: 7346757 (2008-03-01), Hass et al.
patent: 7461213 (2008-12-01), Hass et al.
patent: 7461215 (2008-12-01), Hass
patent: 7467243 (2008-12-01), Rashid et al.
patent: 7509462 (2009-03-01), Hass et al.
patent: 7562362 (2009-07-01), Paquette et al.
patent: 7627721 (2009-12-01), Hass
patent: 2002/0194249 (2002-12-01), Hsieh
patent: 2002/0194250 (2002-12-01), Hsieh
patent: 2003/0037117 (2003-02-01), Tabuchi
patent: 2004/0148606 (2004-07-01), Hosoe
patent: 2004/0215947 (2004-10-01), Ward, III et al.
patent: 2005/0027793 (2005-02-01), Hass
patent: 2005/0033831 (2005-02-01), Rashid
patent: 2005/0033832 (2005-02-01), Hass et al.
patent: 2005/0033889 (2005-02-01), Hass et al.
patent: 2005/0041651 (2005-02-01), Hass et al.
patent: 2005/0041666 (2005-02-01), Hass
patent: 2005/0044308 (2005-02-01), Rashid et al.
patent: 2005/0044323 (2005-02-01), Hass
patent: 2005/0044324 (2005-02-01), Rashid et al.
patent: 2005/0055502 (2005-03-01), Hass et al.
patent: 2005/0055503 (2005-03-01), Hass
patent: 2005/0055504 (2005-03-01), Hass et al.
patent: 2005/0055510 (2005-03-01), Hass et al.
patent: 2005/0055540 (2005-03-01), Hass et al.
patent: 2005/0086361 (2005-04-01), Rashid et al.
patent: 2005/0108711 (2005-05-01), Arnold et al.
patent: 2005/0149936 (2005-07-01), Pilkington
patent: 2006/0056290 (2006-03-01), Hass
patent: 2006/0146864 (2006-07-01), Rosenbluth et al.
patent: 2006/0149927 (2006-07-01), Dagan et al.
patent: 2006/0179281 (2006-08-01), Jensen et al.
patent: 2006/0206692 (2006-09-01), Jensen
Eggers, Susan J.; Emer, Joel S.; Levy, Henry M.; Lo, Jack L.; Stamm, Rebecca L.; Tullsen, Dean M. “Simultaneous Multithreading: A Platform for Next-Generation Processors”. IEEE Micro. © Sep./Oct. 1997. pp. 12-19.
Eggers, Susan J.; Levy, Henry M.; Lo, Jack L.; Tullsen, Dean M. “Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor”. © Jan. 1999. IEEE. Proceedings of Fifth International Symposium on High-Performance Computer Architecture, 1999 pp. 54-58.
Chuang Yu-Chi
Kang Jack
Li Aimee J
Marvell World Trade Ltd.
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