Instruction dependent clock scheme

Details Instruction dependent clock scheme Instruction dependent clock scheme

1997-12-30

2000-12-26

Follansbee, John A.

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

713322, 712229, G06F 104

Patent

active

061675296

ABSTRACT:
A method and apparatus including a first circuit configured to receive multiple instructions including a first instruction having a first execution time, and to generate a first signal having a state dependent on the first execution time; a second circuit configured to receive the first signal and to generate a clock signal including a clock cycle having a period dependent on the state of the first signal; and a third circuit configured to receive the clock signal and execute a portion of the first instruction during the clock cycle, the first execution time corresponding to the portion of the first instruction.

REFERENCES:
patent: 5247656 (1993-09-01), Kabuo et al.

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