Instruction dependency chain indentifier

Details Instruction dependency chain indentifier Instruction dependency chain indentifier

1995-09-06

1998-01-20

Treat, William M.

395393, G06F 938

Patent

active

057109028

ABSTRACT:
A method and apparatus for identifying a sequence of instructions that generate data used by an instruction in a programmed flow of instructions includes a bit array of i lines, where i is an integer, each line representing an instruction in an ordered sequence of instructions. A line in the bit array is made up of a string of bits in which a bit position is set corresponding to a preceding instruction that the instruction is dependent upon. Logic coupled to the bit array generates the string of bits for the next instruction by setting bit positions which correspond to directly dependent instructions and additional bit positions corresponding to the predecessor instructions.

REFERENCES:
patent: 4969117 (1990-11-01), Miranker
patent: 5201057 (1993-04-01), Uht
patent: 5539911 (1996-07-01), Nguyen et al.
"Superscalar Microprocessor Design," by Mike Johnson, Prentice-Hall (1991).

Affiliated with

Also associated with

Rating

Instruction dependency chain indentifier does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Instruction dependency chain indentifier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Instruction dependency chain indentifier will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-732830