Boots – shoes – and leggings
Patent
1989-09-22
1992-03-31
Lee, Thomas C.
Boots, shoes, and leggings
3649315, 3649428, 3649462, 3642624, 364DIG1, 364DIG2, G06F 930
Patent
active
051014831
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a microcomputer including a programmable logic array therein (hereinafter referred to as MC) and a method of testing the same.
BACKGROUND OF THE INVENTION
As illustrated in FIG. 1, a conventional MC includes a data bus, an instruction register IR, a programmable logic array PLA, a data register D, a stack pointer SP, accumlators A, B, temporary registers TRB, TRC, a programmable counter PC, a ROM, and a RAM.
The program counter specifies instructions stored in the ROM, the instructions being sequentially transmitted to the instruction register IR via the data bus.
The PLA includes control output lines connected to internal registers and memories, etc., decodes instruction data transmitted from the IR, and delivers control signals such as an EM (enable memory) signal, a WACC (write accumulator) signal, an EROM (enable read only memory) signal, and a WM (write memory) signal. Those control signals are to switch on and off the internal registers and the memories, and transfer the data stored in the RAM, accumulator, and ROM, etc., onto the data bus or write the data on the data bus in the RAM and accumulator, etc.
The ROM stores instruction codes constituting instructions shown in FIG. 2a and FIG. 2b, for example. An instruction "ADD A, #N", which is represented by an instruction code "1010, 1010" or "A, A", means that the contents stored in the accumulator A are added with #N that is, the contents of the second byte, and then, a result of the addition is stored in the accumulator. An instruction "ADD A, M", which is represented by an instruction code "0110, 0101" or "6, 5", means that the contents stored in the accumulator A are added with the contents stored in the RAM, and then a result of the addition is stored in the accumulator.
The PLA 200 includes, as illustrated in FIG. 32 for example, a plurality of NAND decoders 1, precharge circuits 2, 3, and a sense amplifier 18. The NAND decoder, 1 comprises enhancement FETs indicated by circles (0) as illustrated in FIG. 3b and depression FETs indicated by crosses (x) as illustrated in FIG. 3C. The precharge FET 2 has its one terminal connected to one terminal of the NAND decoder 1 and its other terminal connected to ground. The precharge FET 3 has its one terminal connected to the other terminal of the NAND decoder 1 and its other terminal connected to a power supply V.sub.DD. Those precharge FETs 2, 3 further have their gates connected to precharge signal lines PRC, respectively.
In the following, operation of the PLA circuit shown in FIGS. 3A-3C will be described with reference to timing charts shown in FIGS. 6(a), (b). In a time interval T1 of a timing cycle in an interval M1 of a machine cycle, the control signal EROM opens the output gate of the ROM to fetch out the instruction code stored in the ROM onto the bus and the control signal WIR opens the input gate of the instruction register 100 to store the instruction code on the bus in the instruction register 100. When the instruction code fetched out from the instruction register IR 100 is "A, A", the NAND decoders 1 on decode lines L'1, L'3 become conductive in a machine cycle interval M2 to permit the sense amplifier 18 to input a signal "H" into the AND gate 6. Therefore, in a timing cycle interval T3 the control output signal EACC is generated on a control output signal line 4 via the AND gates 6, and in a timing cycle interval T4 the control output signal WACC is generated. Additionally, when the instruction code is "6, 5", the NAND decoders 1 located on decode lines L'2, L'4 become conductive in a machine cycle interval M2 to permit the sense amplifier 18 to input a signal "H" into the AND gate 6. Therefore, in the timing cycle interval T3 the control output signal ACC is generated on the control output signal line 4, and in a timing cycle interval T4 the control output signal WACC is generated. Here, the control signals such as EROM, WIR, PCUP, and the like illustrated in FIG. 1 are issued from a timing control circuit T/C.
Such a conventional P
REFERENCES:
patent: 3949370 (1976-04-01), Reyling, Jr. et al.
patent: 4835679 (1989-05-01), Kida et al.
Ellis Richard Lee
Lee Thomas C.
OKI Electric Industry Co., Ltd.
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