1979-02-09
1981-02-17
Atkinson, Charles E.
Excavating
307216, G06F 1110
Patent
active
042518849
ABSTRACT:
A parity circuit (FIG. 6) for n signals comprises n-1 parity building blocks (61-67) connected in a parity tree configuration. Each parity building block comprises three interconnected NAND gates (41-43). A first pair of signal inputs (A and B) are connected to the input of the first and second NAND gates (41 and 42), and a second pair of signal inputs (C and D) are connected to the input of the first and third NAND gates (41 and 43). The output of the first NAND gate (41) is coupled to the input of the second and third NAND gates (42 and 43). The pairs of inputs are controlled so that at least one signal in each pair is high ("1").
REFERENCES:
patent: 3602886 (1971-08-01), Carter et al.
patent: 3718904 (1973-02-01), Bulfer et al.
patent: 3838393 (1974-09-01), Dao
patent: 3846751 (1974-11-01), Prieto
patent: 4167727 (1979-09-01), Anderson et al.
Mano, Computer Logic Design, Prentice-Hall, Inc., 1972, pp. 157-159.
Hill and Peterson, Introduction to Switching Theory and Logical Design, John Wiley & Sons, 1974, pp. 199-202.
Atkinson Charles E.
Bell Telephone Laboratories Incorporated
Mullarney John K.
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