Instruction controlling system and method thereof

Details Instruction controlling system and method thereof Instruction controlling system and method thereof

1998-03-17

2000-01-18

Donaghue, Larry D.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Scoreboarding, reservation station, or aliasing

712 23, G06F 1500

Patent

active

060165413

ABSTRACT:
A general-purpose register address output from an instruction register is read and changed to a corresponding register update buffer address in an update table. Additionally, the update reservation instructing bit corresponding to the general-purpose register address is read out from a register update reservation table. If its value is "0", the general-purpose register address is provided to the general-purpose register, and the data stored at that address is input to an arithmetic unit. If the value of the bit is "1", the contents of the corresponding entry in the update table is registered to a reservation station. The reservation station determines the execution order of respective entries, and sequentially provides a register update buffer address to a register update buffer, and inputs the data stored at that address to the arithmetic unit.

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patent: 5881305 (1999-03-01), Walker
patent: 5884061 (1999-03-01), Hesson et al.

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