Instruction control apparatus and method using micro program

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing

Reexamination Certificate

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Details

C712S211000

Reexamination Certificate

active

06789185

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an instruction control apparatus for controlling instructions using a micro program (&mgr; program) in conjunction with an information processing apparatus for sequentially updating/referencing resources (a storage area, register, etc.) accessible from a program in the instruction execution order of the program.
2. Description of the Related Art
A system which is provided with a stack waiting to be processed called a reservation station, for controlling the execution of instructions is well known as a technology for executing instruction processes at high speed in an information processing apparatus. In this system, an out-of-order execution method is adopted, a processible entry in the stack is selected and an instruction is executed as required in an order different from an order designated by a program.
In hardware adopting such an execution method, the decoding of instructions, the operation process in an operation execution unit (E unit), the completion of an instruction execution, etc., are carried out asynchronously. However, in the micro program control of the process of complex instructions, both control synchronized with the operation of an E unit, etc., and an in-order process are needed.
Therefore, in order to perform micro program control in a system adopting an out-of-order execution method, some special mechanism must be provided. However, such a mechanism has not been proposed yet.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an instruction control apparatus for controlling instructions using a micro program, in an information processing apparatus for executing instructions out of order and a method thereof.
In the first aspect of the present invention, the instruction control apparatus comprises a storage device and a control reservation station circuit. The storage device stores a micro program for controlling one or more flows of an instruction process. The control reservation station circuit stores the control information of the micro program for each flow and controls each flow using the control information.
In the second aspect of the present invention, the instruction control apparatus comprises an instruction reservation station circuit and a control reservation station circuit. The instruction reservation station circuit manages an instruction process. The control reservation station circuit stores control information to control the instruction process and controls the instruction process by ouputting control information in synchronization with the instruction process.


REFERENCES:
patent: 5838940 (1998-11-01), Savkar et al.
patent: 5987587 (1999-11-01), Meltzer
patent: 6304953 (2001-10-01), Henstrom et al.
patent: 6502186 (2002-12-01), Inoue
patent: 8-263289 (1996-10-01), None
patent: 7-84965 (1998-06-01), None
patent: 10-154072 (1998-06-01), None
patent: 2000-020306 (2000-01-01), None
Chappell et al., “Simultaneous Subordinate Microthreading (SSMT)”, Proceedings of the 26th International Symposium on Computer Architecture, IEEE, pp. 186-195, May 2, 1999-May 4, 1999.*
Communication for the corresponding Japanese patent application, dated Nov. 4, 2003.

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