Instruction cache memory includes a clock gate circuit for...

Details Instruction cache memory includes a clock gate circuit for... Instruction cache memory includes a clock gate circuit for...

2000-01-06

2002-02-05

Kim, Hong (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S154000, C711S167000, C711S128000, C711S003000, C711S215000, C711S213000, C713S322000

Reexamination Certificate

active

06345336

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an instruction cache memory, and in particular, relates to the instruction cache memory designed to reduce the power consumption.
2. Description of the Related Background Art
Recently, computer systems, in general, are equipped with an instruction cache memory for the purpose of decreasing the memory access latency.
FIG. 7
is a diagram which shows a structure of an instruction cache memory of a conventional direct mapping type.
It will be apparent from
FIG. 7
that the instruction cache memory
100
is made up of data RAM
102
, tag RAM
104
and comparator
106
. An access address is inputted to the instruction cache memory
100
from a fetch counter provided in a processor. Depending upon the size and structure of the instruction cache memory
100
, part of the access address is inputted to the data RAM
102
, and part thereof is inputted to the tag RAM
104
. This conventional technology assumes the use of an instruction cache memory
100
in which data RAM capacity is 1 K words, one cache line size is 8 words, and total number of cache lines is 128. Here, one word is the unit of a single instruction, and it is assumed to be 32 bits in this conventional technology.
In this case, among the access address of 16 bits from the fetch counter, 10 bits totaling low order bits bit
9
through bit
0
are inputted to the data RAM, 7 bits totaling bit
9
through bit
3
are inputted to the tag RAM
104
, and 6 bits totaling high order bits bit
15
to bit
10
are inputted to the comparator
106
. If these bits are expressed in general formulas, those inputted to the data RAM
102
are expressed as bit q-
1
~bit
0
, those inputted to the tag RAM
104
are expressed as bit q-
1
~bit p, and those inputted to the comparator
106
are expressed as bit n-
1
~bit q. In
FIG. 7
, n (number of bits of the access address)=16, p (number of bits necessary for specifying an address in a single cache line)=3, and q (number of bits necessary for specifying an address in the data RAM
102
)=10. The data RAM
102
and the tag RAM
104
are also supplied with a clock signal CLK.
The tag RAM
104
output an access address, which a cache line assigned to the address expressed by bit
9
~bit
3
holds, as a tag signal of 6 bits in total. Also outputted is a status bit of one bit which indicates whether the corresponding cache line has ever taken data from main memory at least once. These tag signal and status bit are inputted into the comparator
106
. The comparator
106
compares the received tag signal of 6 bits with 6 bits totaling bit
15
~bit
10
of the access address. When they coincide, it is a hit. When they do not coincide, it is a miss. Based on the result of the comparison, the comparator
106
outputs a hit/miss judging signal to the processor.
In parallel with the operation of the comparator
106
, data is read out from the data RAM
102
and supplied as an instruction to the processor. Whether or not the processor takes this instruction supplied from the data RAM
102
is determined by whether the hit/miss judging signal of the comparator
106
indicates a cache hit or cache miss. That is, in case of a cache hit, the processor takes this data as an instruction, and in case of a cache miss, the processor does not take this data.
In the cache memory
100
shown in
FIG. 7
, two memories, namely, data RAM
102
and tag RAM
104
, operate upon every time when it is accessed. Therefore, the cache memory
100
involved the problem that it occupied a large part of hardware and consumed large power.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to reduce power consumption of an instruction cache memory. More specifically, the object of the invention lies in alleviating operation of tag RAM in the instruction cache memory and thereby reduce power consumption by the tag RAM.
According to an aspect of the invention, there is provided an instruction cache memory comprising:
data RAM including a plurality of cache lines for storing a plurality of words which have consecutive memory addresses to output read-out data in response to an access address inputted from a processor;
tag RAM for storing data necessary for specifying the memory addresses of the words stored in the cache lines as tag addresses for each cache line of the data RAM, and outputting one of the tag addresses of corresponding one of the cache lines as a tag signal in response to the access address inputted from the processor;
a hit/miss judging circuit for comparing the tag signal outputted from the tag RAM with the access address from the processor to judge whether a word having the memory address corresponding to the access address is stored in the data RAM or not and output a result of the judgement as a hit/miss judging signal; and
a clock gate circuit for supplying a clock signal to the tag RAM only when the cache line for storing the word to be read out changes from one to another, and/or, a branch instruction is detected in the processor, and otherwise stop the supply of the clock signal to the tag RAM.
According to a further aspect of the invention, there is provided an instruction cache memory which is supplied with an access address of n bits from bit n-
1
to bit
0
and a basic clock signal which changes between HIGH and LOW levels in each clock cycle repeatedly in all clock cycles and outputs a hit/miss judging signal of one bit and a read-out data of m bits, comprising:
data RAM including a plurality of cache lines for storing a plurality of words which have a number of consecutive memory addresses which can be expressed by p bits and having a memory size which can be expressed by q bits, the data RAM being supplied with low order bits which are bit q-
1
through bit
0
among n bits of the access address, and outputting the read-out data of m bits;
tag RAM for storing high order bits which are bit n-
1
through bit q among n bits of the memory address of a plurality of words stored in each cache line as a tag address for each cache line, the tag RAM being supplied with bit q-
1
to bit p among n bits of the access address and outputting the tag address stored in association with a cache line specified by bit q-
1
through bit p as a tag signal;
a hit/miss judging circuit supplied with the tag signal outputted from the tag RAM and high order bits which are bit n-
1
through bit q among n bits of the access address to compare the tag signal with the bit n-
1
through bit q and output a hit/miss judging signal of one bit which indicates whether a word having the memory address corresponding to the access address is stored in the data RAM or not; and
a clock gate circuit for supplying a clock signal as a supplied clock signal to the tag RAM only when the cache line for storing the word to be read out changes from one to another, and/or, a branch instruction is detected in the processor, and otherwise stopping the supply of the supplied clock signal to the tag RAM.
According to a still further aspect of the invention, there is provided an instruction cache memory of an x-way set associative mapping type which is supplied with an access address of n bits from bit n-
1
through bit
0
and a basic clock signal which changes between HIGH and LOW levels in each clock cycle repeatedly in all clock cycles and outputs x hit/miss judging signals of one bit and one read-out data of m bits, the cache memory including x basic units each outputting one of the hit/miss judging signal of one bit and one unit read-out data of m bits, each basic unit comprising:
data RAM including a plurality of cache lines for storing a plurality of words having a number of consecutive memory addresses which can be expressed by p bits and having a memory size which can be expressed by q-x-
1
bits, the data RAM being supplied low order bits which are bit q-x through bit
0
among n bits of the access address, and outputting the unit read-out data of m bits;
tag RAM for storing high order bits which are bit n-
1
through bit q-x-
1
among

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