Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-08-25
1999-08-17
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711213, 395383, 395584, 395586, G06F 938
Patent
active
059408570
ABSTRACT:
An instruction cache memory provides a low probability of occurrence of cache error. The instruction cache memory includes an advance read function with an instruction cache for providing/receiving instruction formation in block unit to/from a main memory, an instruction analysis section for predicting whether it is necessary to read out a next block from the main memory by analyzing the instructions included in the block read out from the main memory presently being transferred to the instruction cache, and circuits for reading out the next block from the main memory to transfer to the instruction cache when predicted to be necessary by the instruction analysis section. Prediction is done by judging if a branch predict signal produced within the instruction cache memory is present or not, judging the branch destination to be within the block or in the next block when the branch instruction is detected, and judging whether the branch operation is a forward branch or a backward branch.
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Ando Hideki
Nakanishi Chikako
Chan Eddie P.
Kim Hong
Mitsubishi Denki & Kabushiki Kaisha
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