Instruction cache apparatus and method capable of increasing...

Details Instruction cache apparatus and method capable of increasing... Instruction cache apparatus and method capable of increasing...

2002-04-03

2004-12-28

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S119000, C711S120000, C711S123000, C711S125000, C711S128000, C711S138000, C709S201000, C709S213000, C709S217000, C709S226000, C712S206000, C712S215000, C712S228000

Reexamination Certificate

active

06836828

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention generally relates to an instruction cache apparatus and method, and more particularly, to an instruction cache apparatus and method using the instruction read buffer (IRB).
2. Description of Related Art
The cache memory is mostly composed of the cache instruction word memory and the cache tag memory. The instruction word stored in the cache instruction word memory and the tag stored in the cache tag memory correspond to each other. Therefore, generally, when the CPU needs to access the memory, the cache tag memory is checked to determine whether the tag of the expected instruction word exists or not. If the tag exists, it also means the cache instruction word memory contains the expected instruction word, the so called “instruction hit”. The cache tag memory subsequently issues an instruction hit signal to the cache instruction word memory to read the expected instruction word from the cache instruction word memory. If the tag does not exist, the so called “instruction miss”, the expected instruction word is read from the main memory via the bus interface unit.
Referring to
FIG. 1
, it is known by those skilled in the art that the apparatus and method of the conventional instruction cache is that the cache tag memory
108
,
109
are searched first when it is required to access an instruction word addressed by CPU, to determine whether the tag of the expected instruction word exists. The tag stored in the cache tag memory
108
,
109
is also the tag of the instruction word stored in the cache instruction word memory
106
and the cache instruction word memory
107
. Moreover, the tag stored in the cache tag memory
108
,
109
is compared with the output signal of the programmable counter
115
(this signal includes the tag of the instruction word expected by CPU) by using the comparator
111
and the comparator
112
tightly coupled to the cache tag memory
108
,
109
. If there is a match, the instruction is hit. The comparator
111
subsequently issues an instruction hit signal, so that the multiplexer
104
can proceed with the fetch operation from the cache instruction word memory where the expected instruction word is stored, and subsequently output the needed instruction word.
If there is not a match, the instruction is missed. The CPU issues a request to the main memory through the bus interface unit (BIU)
101
, waits for the main memory to reply to the buffer interface unit
101
, and temporally stores the request in the instruction read buffer
102
. When the bus interface unit
101
replies with an instruction word to the instruction read buffer
102
, it writes the instruction word that was originally stored in the instruction read buffer
102
into the cache instruction word memory
106
or
107
.
Referring to
FIG. 2
, the conventional instruction read buffer
102
is equal to a line in the memory. The line is able to store four instruction words (W
0
, W
1
, W
2
, W
3
). That is, four instruction words can be stored in a line simultaneously at one time. The multiplexer
103
is controlled by the programmable counter
115
and the write-index signal that is the input of the multiplexer
117
. When the next instruction word is going to be stored temporarily in the instruction read buffer
102
, the multiplexer
103
is controlled to write the instruction word into the cache instruction word memory
106
or the cache instruction word memory
107
in a word-by-word manner. Furthermore, the multiplexer
104
fetches the needed instruction word from the cache instruction word memory
106
or the cache instruction word memory
107
for use by the CPU.
Therefore, when the instruction is missed, the CPU has to spend time accomplishing the operation of the expected instruction word assignment.
The time needed is approximately: time needed for the CPU to issue a request to main memory+time needed for the bus interface unit to wait for a reply+time needed for writing into cache instruction word memory+time needed for expected instruction word assignment.
The time needed for the CPU to issue the request to the main memory is about 1~2 clock periods, whereas the time needed for the bus interface unit to wait for the reply is about 10+ clock periods, and when the bus interface unit waits for the reply, the cache instruction word memory is in the idle state. Therefore, the memory management is not efficient.
SUMMARY OF THE INVENTION
In the view of this, the present invention provides a cache apparatus and method using the cache read buffer. The apparatus and method is able to increase the instruction hit rate, and to perform the instruction word write operation when the bus interface unit is waiting for the reply.
The present invention is able to access the instruction word in the cache instruction word memory more efficiently by the addition of an output path, counter and comparator of the instruction read buffer.
The present invention provides an instruction cache apparatus using the cache read buffer. The apparatus comprises an instruction hit analysis unit, an instruction read buffer, a first cache instruction word memory, a second cache instruction word memory, a first multiplexer and a second multiplexer. When the instruction hit analysis unit receives the output signal of the programmable counter, after comparing and analyzing with a plurality of tags, it outputs a signal that includes the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory. The instruction read buffer temporarily stores the instruction word replied by the bus interface unit. The first cache instruction word memory stores the instruction word replied by the bus. The second cache instruction word memory stores the instruction word replied by the bus. The first multiplexer receives a plurality of instruction word output signals of the instruction read buffer. The first multiplexer is controlled via the control signal according to the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory, to write an instruction line, which includes the instruction word and is contained in the instruction read buffer, into the first cache instruction word memory, or to write the instruction line into the second cache instruction word memory, or to output the instruction word that is contained in the instruction read buffer to the second multiplexer. The second multiplexer receives and reads the expected instruction word from the first cache instruction word memory or the second cache instruction word memory or the instruction read register according to the instruction hit signal of the instruction read buffer and the instruction hit signal of the second cache instruction word memory.
The present invention further provides an instruction cache apparatus using the cache read buffer. The apparatus comprises the instruction hit analysis unit, the instruction read buffer, at least a cache instruction word memory, the first multiplexer and the second multiplexer. The instruction hit analysis unit receives the output signal of the programmable counter, and after comparing and analyzing it with a plurality of tags, outputs a signal that includes the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory. The instruction read buffer temporarily stores the instruction word replied by the bus interface unit. The cache instruction word memory stores the instruction word replied by the bus. The first multiplexer receives a plurality of instruction word output signals from the instruction read buffer. The first multiplexer is controlled via the control signal according to the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory, to write an instruction line, which includes the instruction word and is contained in the instruction read buffer, into the

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