Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2007-11-27
2007-11-27
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S320000
Reexamination Certificate
active
10816020
ABSTRACT:
A power management controller for instantaneous frequency-based microprocessor power management including first and second PLLs, select logic, and source control logic. The first PLL generates a first core source clock signal at a first frequency based on a bus clock signal. The second PLL generates a second core source clock signal at a programmable frequency based on a frequency control signal and the bus clock signal. The select logic selects between the first and second core source clock signals to provide a core clock signal for the microprocessor based on a select signal. The source control logic detects power conditions via at least one power sense signal, provides the frequency control signal according to the power conditions, and provides the select signal. The power management controller enables transition from one power state to another in a single clock cycle, which is significantly faster than conventional power management techniques.
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Gaskins Darius D.
Holthaus Charles John
Huffman James W.
Huffman Richard K.
Patel Anand B.
Perveen Rehana
Stanford Gary R.
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