Inspection system and semiconductor device manufacturing method

Details Inspection system and semiconductor device manufacturing method Inspection system and semiconductor device manufacturing method

2001-10-30

2004-08-10

Whitmore, Stacy A. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C702S084000

Reexamination Certificate

active

06775817

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
NOT APPLICABLE
STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
NOT APPLICABLE
REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAM LISTING APPENDIX SUBMITTED ON A COMPACT DISK
NOT APPLICABLE
FIELD OF THE INVENTION
The present invention relates to inspection systems in the manufacture of electronic devices such as semiconductor integrated circuits and also to a methodology for manufacturing electronic devices using this inspection system.
BACKGROUND OF THE INVENTION
In the manufacture of electronic devices typically including semiconductor integrated circuits, after detection of defects using, for example, a dark-field and/or bright-field wafer inspection apparatus, an image taking apparatus with a built-in electron microscope or a similar review apparatus is used in some cases for analyzing the individual defects thus detected. It should be noted that while a dark-field wafer inspection apparatus detects particles attached to wafers, and a bright field wafer inspection apparatus detects pattern defects formed on wafers, such particles and pattern defects will be termed “defects” in the following description.
Currently available review apparatuses are generally designed to sense or pick up the position of an individual defect as an image having higher resolution than is available using dark-field and bright-field wafer inspection apparatuses. Because of this characteristic, such review apparatuses are not for imaging the positions of all possible defects detected by an inspection apparatus but for sampling the defect positions within wafer surfaces and for performing image sensing operations with respect only to several limited surface areas. Traditionally this sampling has been achieved by random sampling—that is, random selection of defects from among those defects detected.
In addition, Published Unexamined Japanese Patent Application No. 10-214866 (“JP-A-10-214866”) discloses a technique, in cases where cluster-shaped defects (such as scars) and clustered defects or the like are present, for classifying those defects into defects occurring inside or outside the cluster-like defects. In this case, too, random sampling of several portions from the inside of the cluster-like defects was done while randomly sampling several portions from the outside.
With the prior art random sampling technique, although it is possible to statistically recognize the tendency of defects, the current technologies cannot ensure efficient review of any required defects. For example, it is impossible to provide any priority-added remedy for critical defects that can lead to electrical failures, which, in turn, makes it difficult to effectively improve the resultant yield of production.
SUMMARY OF THE INVENTION
It is therefore a primary aim of the present invention to provide an inspection system capable of improving inspection efficiency by determining certain defects to warrant high-priority review. Another aim is to improve thereby the manufacturing yield of semiconductor devices.
We have taken into careful consideration the relationship of a defect distribution and Large Scale Integration chip (hereinafter “LSI”) layout, and propose a specific technique for enabling selection of defects to be given high-priority review.
FIG. 10
is a diagram showing a distribution of defects within the chip to be detected by the inspection apparatus.
This diagram shows the superimposition of dots
35
, which represent data about defects detected by the inspection apparatus, onto a schematic diagram
32
of the circuit layout of an LSI chip. More specifically, the detected defects are placed on the LSI schematic diagram using position coordinates within each LSI chip on a wafer. Black dots represent the individual defects. Rectangular frames B
1
-B
7
are the positions of LSI blocks
1
-
7
, respectively. The term “SI block” as used herein refers to an A/D converter block, D/A converter block, memory block, processor block, or the like, in mobile wireless telephone handsets, by way of example. LSI blocks are generally called circuit blocks, which have independent functions within an LSI and their layout is also separate, except for electrical connection of circuits used therein.
As is apparent from the diagram, a distribution of defects detected by the inspection apparatus is closely related to the circuit layout, and exhibits the characteristics which follow.
(1) Defect density is different depending upon the circuit pattern density of the circuit layout. In a region in which the circuit layout is coarse and rough, a greater number of defects will be detected than in dense regions. Generally, the coarse density of circuit pattern differs in units of LSI blocks; for example, processor blocks are narrower in circuit pattern width than memory blocks but have greater layout density. Hence, an increased number of defects are detected in processor blocks than in memory blocks.
(2) At the LSI block edges (contour parts of the circuit layout), a great number of defects are detected. In many cases, this is because the inspection apparatus erroneously identifies as defects objects which are actually not defects. These detection errors occur in areas with greater convex-concave differences in the circuit pattern. Here, the term “edge portion (contour part)” is used to mean a boundary between circuit blocks, which boundary has widths ranging from several tens to several hundreds of micrometers.
Thus, selection through simple random sampling of defects to be reviewed creates another problem: inability to efficiently sample such defects as review candidates, e.g., those defects which have a higher probability of becoming electrical failures.
The present invention resolves the foregoing problems by employing a unique technique using an LSI's design layout to select defects for review. More specifically, LSI design layout information is used to give higher review priority to certain defects that are not in close proximity to LSI block contour portions, or, alternatively, to give higher review priority to defects present in LSI blocks of dense circuit pattern widths.
Moreover, the present invention uses a technique for obtaining failure probability (kill ratio) relative to defect size in the units of LSI blocks and for reviewing high-failure-probability defects. Specified defects most likely to influence production yield are reviewed first, which, in turn, makes it easier and faster to inquire about and clarify several factors having direct influence on production yield in a shorter period of time, thus improving the manufacturing yield. In particular, with a specific type of product having a variety of circuit blocks present in a single LSI, such as the system LSIs, permitting certain defects to be reviewed with higher priority is important for improving yields at earlier stages of the manufacturing process.


REFERENCES:
patent: 4618938 (1986-10-01), Sandland et al.
patent: 5539514 (1996-07-01), Shishido et al.
patent: 5598341 (1997-01-01), Ling et al.
patent: 5777901 (1998-07-01), Berezin et al.
patent: 6047083 (2000-04-01), Mizuno
patent: 6128403 (2000-10-01), Ozaki
patent: 6169960 (2001-01-01), Ehrichs
patent: 6272236 (2001-08-01), Pierrat et al.
patent: 6324481 (2001-11-01), Atchison et al.
patent: 6334209 (2001-12-01), Hashimoto et al.
patent: 6393602 (2002-05-01), Atchison et al.
patent: 6401235 (2002-06-01), Ashida
patent: 6411377 (2002-06-01), Noguchi et al.
patent: 6438438 (2002-08-01), Takagi et al.
patent: 6507933 (2003-01-01), Kirsch et al.
patent: 6539272 (2003-03-01), Ono et al.
patent: 2001/0020194 (2001-09-01), Takagi et al.
patent: 10-214866 (1998-08-01), None

Affiliated with

Also associated with

Rating

Inspection system and semiconductor device manufacturing method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Inspection system and semiconductor device manufacturing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Inspection system and semiconductor device manufacturing method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3302529